{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T17:18:06Z","timestamp":1782926286012,"version":"3.54.5"},"reference-count":32,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"},{"start":{"date-parts":[[2021,11,1]],"date-time":"2021-11-01T00:00:00Z","timestamp":1635724800000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by\/4.0\/legalcode"}],"funder":[{"DOI":"10.13039\/501100001602","name":"Science Foundation Ireland","doi-asserted-by":"publisher","award":["14\/RP\/I2921"],"award-info":[{"award-number":["14\/RP\/I2921"]}],"id":[{"id":"10.13039\/501100001602","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,11]]},"DOI":"10.1109\/jssc.2021.3101046","type":"journal-article","created":{"date-parts":[[2021,8,11]],"date-time":"2021-08-11T20:13:42Z","timestamp":1628712822000},"page":"3445-3457","source":"Crossref","is-referenced-by-count":31,"title":["A Reference-Waveform Oversampling Technique in a Fractional-N ADPLL"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4533-3576","authenticated-orcid":false,"given":"Jianglin","family":"Du","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1658-9596","authenticated-orcid":false,"given":"Teerachot","family":"Siriburanon","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3685-7666","authenticated-orcid":false,"given":"Yizhe","family":"Hu","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Vivek","family":"Govindaraj","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9848-1129","authenticated-orcid":false,"given":"Robert Bogdan","family":"Staszewski","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2015.7063029"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162917"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2843337"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2020.3008298"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032723"},{"key":"ref12","first-page":"174","article-title":"9.6 A 2.7-to-4.3 GHz, 0.16 ${\\text {ps}_{rms}}$\n-jitter,- 246.8 dB-FOM, digital fractional-N sampling PLL in 28 nm CMOS","author":"gao","year":"2016","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref13","first-page":"258","article-title":"16.2 A 76${\\text {fs}_{rms}}$\n jitter and ?40dBc integrated-phase-noise 28-to-31GHz frequency synthesizer based on digital sub-sampling PLL using optimally spaced voltage comparators and background loop-gain optimization","author":"kim","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2403373"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2889690"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778010"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2020.3025142"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2053094"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2529004"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/4.848214"},{"key":"ref4","first-page":"172","article-title":"9.8 An $860\\mu\\text{W}$\n 2.1-to-2.7GHz alldigital PLL-based frequency modulator with a DTC-assisted snapshot TDC for WPAN (Bluetooth Smart and ZigBee) applications","author":"chillara","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2019.8902523"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2878836"},{"key":"ref6","first-page":"152","article-title":"8.6 A 2.5-to-5.75 GHz 5 mW 0.3${\\text {ps}_{rms}}$\n-jitter cascaded ring-based digital injection-locked clock multiplier in 65 nm CMOS","author":"coombs","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref29","first-page":"420","article-title":"24.7 a 673 $\\mu\\text{W}$\n 1.8-to-2.5 GHz dividerless fractional-N digital PLL with an inherent frequency-capture capability and a phase-dithering spur mitigation for IoT applications","author":"he","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2385753"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2872539"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899726"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2682841"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2546304"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.836345"},{"key":"ref20","first-page":"270","article-title":"16.8 A 25.4-to-29.5 GHzz 10.2 mw isolated sub-sampling PLL achieving-252.9dB jitter-power FoM and-63dbc reference spur","author":"yang","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","first-page":"1","article-title":"A 7.7 10.3 GHz 5.2 mW ?247.3 dB-FOM fractional-N reference sampling PLL with 2nd order CDAC based fractional spur cancellation in 45 nm CMOS","author":"liao","year":"2020","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1002\/0470041951"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2007.916845"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2822823"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2878830"},{"key":"ref25","first-page":"246","article-title":"A 9.4-ENOB 1V $3.8\\mu\\text{W}$\n 100kS\/s SAR ADC with time-domain comparator","author":"agnes","year":"2008","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9583614\/09511426.pdf?arnumber=9511426","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,2,7]],"date-time":"2022-02-07T20:49:30Z","timestamp":1644266970000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9511426\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,11]]},"references-count":32,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2021.3101046","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,11]]}}}