{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,2]],"date-time":"2026-05-02T14:56:28Z","timestamp":1777733788629,"version":"3.51.4"},"reference-count":26,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2022,1]]},"DOI":"10.1109\/jssc.2021.3109167","type":"journal-article","created":{"date-parts":[[2021,9,10]],"date-time":"2021-09-10T20:28:45Z","timestamp":1631305725000},"page":"32-43","source":"Crossref","is-referenced-by-count":51,"title":["A 112-Gb\/s PAM-4 Low-Power Nine-Tap Sliding-Block DFE in a 7-nm FinFET Wireline Receiver"],"prefix":"10.1109","volume":"57","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7445-2232","authenticated-orcid":false,"given":"James","family":"Bailey","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6247-512X","authenticated-orcid":false,"given":"Hossein","family":"Shakiba","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1148-690X","authenticated-orcid":false,"given":"Ehud","family":"Nir","sequence":"additional","affiliation":[]},{"given":"Grigory","family":"Marderfeld","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7180-0396","authenticated-orcid":false,"given":"Peter","family":"Krotnev","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6868-6294","authenticated-orcid":false,"given":"Marc-Andre","family":"LaCroix","sequence":"additional","affiliation":[]},{"given":"David","family":"Cassan","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7319-143X","authenticated-orcid":false,"given":"Davide","family":"Tonietto","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref1","volume-title":"Cisco Annual Internet Report (2018\u20132023)","year":"2020"},{"key":"ref2","volume-title":"Long Reach Interface, Optical Internetworking Forum (OIF)","year":"2020"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9366030"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063081"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2959511"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3051109"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062925"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/49.87640"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2004.842935"},{"key":"ref10","volume-title":"VLSI Digital Signal Processing Systems: Design and Implementation","author":"Parhi","year":"1999"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2018.2844603"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2878850"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937519"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2013.6572453"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365929"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/4.585246"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/OJCAS.2020.3040947"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/OJCAS.2020.3041239"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365853"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.21236\/ada605735"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/MASSP.1985.1163741"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/20.617726"},{"key":"ref23","volume-title":"Exploration on the Worst Case DFE Weight of DFE Error Propagation Effect","author":"Lu","year":"2019"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2943569"},{"key":"ref25","volume-title":"RS(544,514) FEC Performance With 4:1 Interleaving (Updated 2)","author":"Anslow","year":"2018"},{"key":"ref26","volume-title":"Design Compiler User Guide Version N-2017.09","year":"2017"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9664397\/09535163.pdf?arnumber=9535163","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,11]],"date-time":"2024-01-11T22:42:03Z","timestamp":1705012923000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9535163\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,1]]},"references-count":26,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2021.3109167","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,1]]}}}