{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,30]],"date-time":"2026-04-30T16:26:34Z","timestamp":1777566394438,"version":"3.51.4"},"reference-count":41,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"12","license":[{"start":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T00:00:00Z","timestamp":1638316800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T00:00:00Z","timestamp":1638316800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,12,1]],"date-time":"2021-12-01T00:00:00Z","timestamp":1638316800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2021,12]]},"DOI":"10.1109\/jssc.2021.3111134","type":"journal-article","created":{"date-parts":[[2021,9,21]],"date-time":"2021-09-21T20:11:24Z","timestamp":1632255084000},"page":"3756-3767","source":"Crossref","is-referenced-by-count":137,"title":["A 14-nm Ultra-Low Jitter Fractional-<i>N<\/i> PLL Using a DTC Range Reduction Technique and a Reconfigurable Dual-Core VCO"],"prefix":"10.1109","volume":"56","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6425-5294","authenticated-orcid":false,"given":"Wanghua","family":"Wu","sequence":"first","affiliation":[{"name":"Samsung Semiconductor, San Jose, CA, USA"}]},{"given":"Chih-Wei","family":"Yao","sequence":"additional","affiliation":[{"name":"Samsung Semiconductor, San Jose, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6279-2128","authenticated-orcid":false,"given":"Chengkai","family":"Guo","sequence":"additional","affiliation":[{"name":"Samsung Semiconductor, San Jose, CA, USA"}]},{"given":"Pei-Yuan","family":"Chiang","sequence":"additional","affiliation":[{"name":"Samsung Semiconductor, San Jose, CA, USA"}]},{"given":"Lei","family":"Chen","sequence":"additional","affiliation":[{"name":"Samsung Semiconductor, San Jose, CA, USA"}]},{"given":"Pak-Kim","family":"Lau","sequence":"additional","affiliation":[{"name":"Samsung Semiconductor, San Jose, CA, USA"}]},{"given":"Zhanjun","family":"Bai","sequence":"additional","affiliation":[{"name":"Samsung Semiconductor, San Jose, CA, USA"}]},{"given":"Sang Won","family":"Son","sequence":"additional","affiliation":[{"name":"Samsung Semiconductor, San Jose, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8053-6491","authenticated-orcid":false,"given":"Thomas Byunghak","family":"Cho","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Hwaseong-si, South Korea"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/SMIC.2008.30"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/4.972142"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/4.848214"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/LMWC.2013.2248080"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2017.7993633"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2539344"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/PROC.1966.4682"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2414421"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1002\/9780470374122"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162917"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063024"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC49505.2020.9218380"},{"key":"ref40","first-page":"264","article-title":"16.5 A fractional-N synthesizer with 110fs??? jitter and a reference quadrupler for wideband 802.11ax","author":"song","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2967562"},{"key":"ref13","first-page":"270","article-title":"16.8 A 25.4-to-29.5GHz 10.2 mW isolated sub-sampling PLL achieving ?252.9dB jitter-power FoM and -63dBc reference spur","author":"yang","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032723"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3019344"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899726"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063135"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/4.229400"},{"key":"ref19","first-page":"174","article-title":"A 2.7-to-4.3GHz 0.16 ps rms jitter, ?246.8 dB FOM digital fractional-N sampling PLL in 28nm CMOS","author":"gao","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/19.87022"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2016.2647698"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/4.494195"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/COMST.2020.3012715"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2019.8902919"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2742518"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2878836"},{"key":"ref8","first-page":"378","article-title":"A 7.4-to-14GHz PLL with 54fs??? jitter in 16nm FinFET for integrated RF-data-converter SoCs","author":"turker","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref7","first-page":"451","article-title":"32.6 A K-band 12.1-to-16.6GHz subsampling ADPLL with 47.3fs??? jitter based on a stochastic flash TDC and coupled dual-core DCO in 16nm FinFET CMOS","author":"thaller","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2820149"},{"key":"ref9","first-page":"258","article-title":"16.2 A 76fs??? jitter and ?40dBc integrated-phase-noise 28-to-31GHz frequency synthesizer based on digital sub-sampling PLL using optimally spaced voltage comparators and background loop-gain optimization","author":"kim","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref1","year":"2020","journal-title":"Study on Support of NR Downlink 256 Quadrature Amplitude Modulation (QAM) for Frequency Range 2 (FR2)"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2596766"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC.2014.6942026"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2940332"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365850"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2314436"},{"key":"ref41","first-page":"266","article-title":"A calibration-free triple-loop bang-bang PLL achieving 131fs??? jitter and ?70dBc fractional spurs","author":"yang","year":"0","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310341"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2865460"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9625642\/09541410.pdf?arnumber=9541410","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,12,11]],"date-time":"2024-12-11T01:19:47Z","timestamp":1733879987000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9541410\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,12]]},"references-count":41,"journal-issue":{"issue":"12"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2021.3111134","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2021,12]]}}}