{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,25]],"date-time":"2026-07-25T16:19:51Z","timestamp":1784996391683,"version":"3.55.0"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,1,1]],"date-time":"2022-01-01T00:00:00Z","timestamp":1640995200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS 17-19235"],"award-info":[{"award-number":["CNS 17-19235"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"National Science Foundation","doi-asserted-by":"publisher","award":["CNS 19-35573"],"award-info":[{"award-number":["CNS 19-35573"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2022,1]]},"DOI":"10.1109\/jssc.2021.3113335","type":"journal-article","created":{"date-parts":[[2021,10,2]],"date-time":"2021-10-02T02:22:43Z","timestamp":1633141363000},"page":"167-181","source":"Crossref","is-referenced-by-count":33,"title":["Syn-STELLAR: An EM\/Power SCA-Resilient AES-256 With Synthesis-Friendly Signature Attenuation"],"prefix":"10.1109","volume":"57","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-7842-030X","authenticated-orcid":false,"given":"Archisman","family":"Ghosh","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1843-0124","authenticated-orcid":false,"given":"Debayan","family":"Das","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5837-1304","authenticated-orcid":false,"given":"Josef","family":"Danial","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5207-1079","authenticated-orcid":false,"given":"Vivek","family":"De","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0069-7971","authenticated-orcid":false,"given":"Santosh","family":"Ghosh","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5566-8946","authenticated-orcid":false,"given":"Shreyas","family":"Sen","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-125"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-29485-8_13"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-68697-5_9"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-011-0006-y"},{"key":"ref5","first-page":"1","article-title":"X-DeepSCA: Cross-device deep learning side channel attack","volume-title":"Proc. 56th ACM\/IEEE Design Automat. Conf. (DAC)","author":"Das"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2019.2926324"},{"key":"ref7","volume-title":"TEMPEST Attacks Against AES","year":"2015"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2009.4977309"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034081"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662344"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2822691"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062997"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3032975"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/VLSICircuits18222.2020.9162988"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3052146"},{"key":"ref16","first-page":"403","article-title":"A dynamic and differential CMOS logic with signal independent power consumption to withstand differential power analysis on smart cards","volume-title":"Proc. Eur. Solid-State Circuits","author":"Tiri"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/11894063_19"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.870913"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-74735-2_6"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1007\/s00145-010-9086-6"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1088\/1674-4926\/33\/6\/065009"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2945944"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2017.7951799"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2819499"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2019.8740839"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-44499-8_5"},{"key":"ref27","first-page":"29","article-title":"The EM side\u2014Channel(s)","volume-title":"Proc. 4th Int. Workshop Cryptograph. Hardw. Embedded Syst. (CHES)","author":"Agrawal"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/4\/9664397\/9555816-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9664397\/09555816.pdf?arnumber=9555816","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,11]],"date-time":"2024-01-11T22:44:53Z","timestamp":1705013093000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9555816\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,1]]},"references-count":27,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2021.3113335","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,1]]}}}