{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,10]],"date-time":"2026-03-10T09:23:54Z","timestamp":1773134634854,"version":"3.50.1"},"reference-count":67,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,4,1]],"date-time":"2022-04-01T00:00:00Z","timestamp":1648771200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2022,4]]},"DOI":"10.1109\/jssc.2022.3140753","type":"journal-article","created":{"date-parts":[[2022,1,24]],"date-time":"2022-01-24T20:52:04Z","timestamp":1643057524000},"page":"1013-1026","source":"Crossref","is-referenced-by-count":59,"title":["CHIMERA: A 0.92-TOPS, 2.2-TOPS\/W Edge AI Accelerator With 2-MByte On-Chip Foundry Resistive RAM for Efficient Training and Inference"],"prefix":"10.1109","volume":"57","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4179-1692","authenticated-orcid":false,"given":"Kartik","family":"Prabhu","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"given":"Albert","family":"Gural","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"given":"Zainab F.","family":"Khan","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"given":"Robert M.","family":"Radway","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7012-4135","authenticated-orcid":false,"given":"Massimo","family":"Giordano","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"given":"Kalhan","family":"Koul","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"given":"Rohan","family":"Doshi","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7860-8302","authenticated-orcid":false,"given":"John W.","family":"Kustin","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"given":"Timothy","family":"Liu","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"given":"Gregorio B.","family":"Lopes","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"given":"Victor","family":"Turbiner","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"given":"Win-San","family":"Khwa","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan"}]},{"given":"Yu-Der","family":"Chih","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan"}]},{"given":"Meng-Fan","family":"Chang","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company (TSMC), Hsinchu, Taiwan"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5223-6582","authenticated-orcid":false,"given":"Guenole","family":"Lallement","sequence":"additional","affiliation":[{"name":"Reality Labs, Meta Platforms, Inc, Sunnyvale, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3417-8782","authenticated-orcid":false,"given":"Boris","family":"Murmann","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5572-5194","authenticated-orcid":false,"given":"Subhasish","family":"Mitra","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8834-8663","authenticated-orcid":false,"given":"Priyanka","family":"Raina","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Stanford University, Stanford, CA, USA"}]}],"member":"263","reference":[{"key":"ref39","first-page":"1","article-title":"A high-performance low-power highly manufacturable embedded DRAM technology using backend hi-$k$ MIM capacitor at 40 nm node and beyond","author":"chen","year":"2011","journal-title":"Proc Int Symp VLSI Technol Syst Appl"},{"key":"ref38","first-page":"198c","article-title":"A 40 nm split gate embedded flash macro with flexible 2-in-1 architecture, code memory with 140 MHz read speed and data memory with 1M cycles endurance","author":"yu","year":"2017","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062989"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-020-00515-3"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492347"},{"key":"ref30","author":"grzywaczewski","year":"2017","journal-title":"Training AI for Self-Driving Vehicles The Challenge of Scale"},{"key":"ref37","first-page":"1","article-title":"40 nm embedded self-aligned split-gate flash technology for high-density automotive microcontrollers","author":"shum","year":"2017","journal-title":"Proc IEEE Int Memory Workshop (IMW)"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1016\/j.sysarc.2011.01.005"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2015.7059057"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662447"},{"key":"ref60","first-page":"1","article-title":"Random soft error suppression by stoichiometric engineering: CMOS compatible and reliable 1 Mb HfO2-ReRAM with 2 extra masks for embedded IoT systems","author":"ho","year":"2016","journal-title":"Proc IEEE Symp VLSI Technol"},{"key":"ref62","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2019.2894387"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2882603"},{"key":"ref63","article-title":"Hyper-parameter optimization: A review of algorithms and applications","author":"yu","year":"2020","journal-title":"arXiv 2003 05689"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/COMST.2020.3007787"},{"key":"ref64","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-60577-3_21"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/FMEC49853.2020.9144755"},{"key":"ref65","article-title":"A scalable and cloud-native hyperparameter tuning system","author":"george","year":"2020","journal-title":"arXiv 2006 02085"},{"key":"ref66","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2871623"},{"key":"ref29","year":"2021","journal-title":"Migration to Google Cloud Transferring Your Large Datasets"},{"key":"ref67","first-page":"246","article-title":"14.5 envision: A 0.26-to-10 TOPS\/W subword-parallel dynamic-voltage-accuracy-frequency-scalable convolutional neural network processor in 28 nm FDSOI","author":"moons","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3140659.3080246"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0059-3"},{"key":"ref20","first-page":"1","article-title":"SamurAI: A 1.7 MOPS–36 GOPS adaptive versatile IoT node with 15,000$\\times$ peak-to-idle power reduction, 207 ns wake-up time and 1.3 TOPS\/W ML efficiency","author":"miro-panades","year":"2020","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2960488"},{"key":"ref21","year":"2021","journal-title":"Edge TPU"},{"key":"ref24","first-page":"1","article-title":"Low-rank training of deep neural networks for emerging memory technology","volume":"abs 2009 3887","author":"gural","year":"2020","journal-title":"CoRR"},{"key":"ref23","first-page":"1","article-title":"An all-weights-on-chip DNN accelerator in 22 nm ULL featuring $24\\times1$ Mb eRRAM","author":"wang","year":"2020","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1016\/B978-044482250-5\/50015-3"},{"key":"ref25","article-title":"Federated learning for mobile keyboard prediction","author":"hard","year":"2018","journal-title":"arXiv 1811 03604"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2020.2996616"},{"key":"ref51","author":"torng","year":"2021","journal-title":"Mflowgen"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662302"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPSW.2019.00148"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778056"},{"key":"ref56","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref55","year":"2004","journal-title":"Catapult-C Manual and C\/C++ Style Guide"},{"key":"ref54","doi-asserted-by":"publisher","DOI":"10.1145\/3373376.3378514"},{"key":"ref53","first-page":"226","article-title":"A 43 pJ\/cycle non-volatile microcontroller with 4.7 $\\mu$\ns shutdown\/wake-up integrating 2.3-bit\/cell resistive RAM and resilience techniques","author":"wu","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref52","first-page":"478","article-title":"An N40 $256 K\\times44$\n embedded RRAM macro with SL-precharge SA and low-voltage current limiter to improve read and write performance","author":"chou","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2910232"},{"key":"ref11","first-page":"247","article-title":"Where’s the bear?—Automating wildlife image processing using IoT and edge cloud systems","author":"elias","year":"2017","journal-title":"Proc IEEE\/ACM 2nd Int Conf Internet-of-Things Design Implement (IoTDI)"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-018-0117-x"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2019.2942092"},{"key":"ref13","article-title":"Optimizing speech recognition for the edge","author":"shangguan","year":"2019","journal-title":"arXiv 1909 12408"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-030-32813-9_3"},{"key":"ref15","article-title":"MIMIC-III, a freely accessible critical care database","volume":"3","author":"johnson","year":"2016","journal-title":"Data Science Journal"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JBHI.2016.2633287"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.23919\/ChiCC.2018.8483118"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.2991\/ifmeita-16.2016.105"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2019.2947125"},{"key":"ref4","year":"2021","journal-title":"Groq"},{"key":"ref3","year":"2021","journal-title":"Graphcore"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358302"},{"key":"ref5","year":"2021","journal-title":"Cerebra"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/COMST.2018.2844341"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2019.2921977"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2018.8573527"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3297858.3304011"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1038\/nature22994"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1109\/LED.2021.3055017"},{"key":"ref48","article-title":"The rocket chip generator","author":"asanovic","year":"2016"},{"key":"ref47","first-page":"27.4.1","article-title":"Monolithic 3D integration of logic and memory: Carbon nanotube FETs, resistive RAM, and silicon FETs","author":"shulaker","year":"2014","journal-title":"IEDM Tech Dig"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1038\/nnano.2015.29"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993514"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2016.2546199"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/4\/9741814\/9690772-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9741814\/09690772.pdf?arnumber=9690772","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,5,16]],"date-time":"2022-05-16T20:17:06Z","timestamp":1652732226000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9690772\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,4]]},"references-count":67,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2022.3140753","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,4]]}}}