{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,9]],"date-time":"2026-04-09T14:31:10Z","timestamp":1775745070533,"version":"3.50.1"},"reference-count":37,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2022,9,1]],"date-time":"2022-09-01T00:00:00Z","timestamp":1661990400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,9,1]],"date-time":"2022-09-01T00:00:00Z","timestamp":1661990400000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2022,9,1]],"date-time":"2022-09-01T00:00:00Z","timestamp":1661990400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2022,9,1]],"date-time":"2022-09-01T00:00:00Z","timestamp":1661990400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2022,9]]},"DOI":"10.1109\/jssc.2022.3163197","type":"journal-article","created":{"date-parts":[[2022,4,12]],"date-time":"2022-04-12T19:35:11Z","timestamp":1649792111000},"page":"2868-2877","source":"Crossref","is-referenced-by-count":56,"title":["A 40-nm MLC-RRAM Compute-in-Memory Macro With Sparsity Control, On-Chip Write-Verify, and Temperature-Independent ADC References"],"prefix":"10.1109","volume":"57","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8288-393X","authenticated-orcid":false,"given":"Wantong","family":"Li","sequence":"first","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5337-5680","authenticated-orcid":false,"given":"Xiaoyu","family":"Sun","sequence":"additional","affiliation":[{"name":"Taiwan Semiconductor Manufacturing Company (TSMC), San Jose, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1760-7656","authenticated-orcid":false,"given":"Shanshi","family":"Huang","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3048-5948","authenticated-orcid":false,"given":"Hongwu","family":"Jiang","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0068-3652","authenticated-orcid":false,"given":"Shimeng","family":"Yu","sequence":"additional","affiliation":[{"name":"School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA, USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/nature14539"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2616357"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870353"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3079856.3080246"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2778702"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870350"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2018.2790840"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1038\/s41565-020-0655-z"},{"key":"ref9","first-page":"242","article-title":"A 351TOPS\/W and 372.4GOPS compute-in-memory SRAM macro in 7 nm FinFET CMOS for machine-learning applications","volume-title":"IEEE ISSCC Dig. Tech. Papers","author":"Dong"},{"key":"ref10","first-page":"496","article-title":"A 65 nm 4 Kb algorithm-dependent computing-in-memory SRAM unit-macro with 2.3 ns and 55.8TOPS\/W fully parallel product-sum operation for binary DNN edge processors","volume-title":"IEEE ISSCC Dig. Tech. Papers","author":"Khwa"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510687"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492444"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2782087"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2012.2190369"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3072200"},{"key":"ref16","first-page":"388","article-title":"A 1 Mb multibit ReRAM computing-in-memory macro with 14.6 ns parallel MAC computing time for CNN based AI edge processors","volume-title":"IEEE ISSCC Dig. Tech. Papers","author":"Xue"},{"key":"ref17","first-page":"245","article-title":"A 22 nm 4 Mb 8b-precision ReRAM computing-in-memory macro with 11.91 to 195.7TOPS\/W for tiny AI edge devices","volume-title":"IEEE ISSCC Dig. Tech. Papers","author":"Xue"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIT.2018.8510676"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/CICC51472.2021.9431558"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062979"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.3015178"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3101209"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1038\/nature14441"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-020-0397-9"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2020.2992228"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-020-1942-4"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2020.3010795"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ESSDERC53440.2021.9631810"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1088\/1361-6641\/abb842"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2019.2943047"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19573.2019.8993491"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2019.2933148"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2020.2985013"},{"key":"ref34","first-page":"1","article-title":"Training and inference with integers in deep neural networks","volume-title":"Proc. Int. Conf. Learn. Representative (ICLR)","author":"Wu"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2017.7952679"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/MDAT.2021.3050715"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS45731.2020.9181022"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/4\/9866858\/9755965-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/9866858\/09755965.pdf?arnumber=9755965","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,1,22]],"date-time":"2024-01-22T21:08:09Z","timestamp":1705957689000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9755965\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2022,9]]},"references-count":37,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2022.3163197","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2022,9]]}}}