{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,26]],"date-time":"2026-09-26T17:03:50Z","timestamp":1790442230076,"version":"4.1.0"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"6","license":[{"start":{"date-parts":[[2023,6,1]],"date-time":"2023-06-01T00:00:00Z","timestamp":1685577600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,6,1]],"date-time":"2023-06-01T00:00:00Z","timestamp":1685577600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,6,1]],"date-time":"2023-06-01T00:00:00Z","timestamp":1685577600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001809","name":"National Natural Science Foundation of China","doi-asserted-by":"publisher","award":["62122001"],"award-info":[{"award-number":["62122001"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003009","name":"Science and Technology Development Fund","doi-asserted-by":"publisher","award":["0093\/2019\/A2"],"award-info":[{"award-number":["0093\/2019\/A2"]}],"id":[{"id":"10.13039\/501100003009","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003009","name":"Science and Technology Development Fund","doi-asserted-by":"publisher","award":["SKL-AMSV(UM)-2020-2022"],"award-info":[{"award-number":["SKL-AMSV(UM)-2020-2022"]}],"id":[{"id":"10.13039\/501100003009","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2023,6]]},"DOI":"10.1109\/jssc.2022.3213835","type":"journal-article","created":{"date-parts":[[2022,11,3]],"date-time":"2022-11-03T22:36:20Z","timestamp":1667514980000},"page":"1758-1768","source":"Crossref","is-referenced-by-count":44,"title":["An SC-Parallel-Inductor Hybrid Buck Converter With Reduced Inductor Voltage and Current"],"prefix":"10.1109","volume":"58","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-8204-8870","authenticated-orcid":false,"given":"Guigang","family":"Cai","sequence":"first","affiliation":[{"name":"State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and FST-DECE, University of Macau, Macau, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9273-7576","authenticated-orcid":false,"given":"Yan","family":"Lu","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and FST-DECE, University of Macau, Macau, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2821-648X","authenticated-orcid":false,"given":"Rui P.","family":"Martins","sequence":"additional","affiliation":[{"name":"State Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and FST-DECE, University of Macau, Macau, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2018.2793163"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2880183"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/CICC48029.2020.9075902"},{"key":"ref15","first-page":"146","article-title":"A 93.8% peak efficiency, 5 V-input, 10 A max ILOAD flying capacitor multilevel converter in 22 nm CMOS featuring wide output voltage range and flying capacitor precharging","author":"schaef","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2018.2843777"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/81.678481"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2016.2556098"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2755683"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870321"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2169309"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2007.915182"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2617315"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"2120","DOI":"10.1109\/JSSC.2011.2159054","article-title":"Design techniques for fully integrated switched-capacitor DC–DC converters","volume":"46","author":"le","year":"2011","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3053457"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3004256"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9366016"},{"key":"ref18","first-page":"256","article-title":"A two-stage cascaded hybrid switched-capacitor DC–DC converter with 96.9% peak efficiency tolerating 0.6 V\/?s input slew rate during startup","author":"xia","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref24","first-page":"152","article-title":"Fully integrated buck converter with 78% efficiency at 365 mW output power enabled by switched-inductor capacitor topology and inductor current reduction technique","author":"tang","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2944837"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/APEC42165.2021.9487174"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2882526"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2957658"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063105"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3044062"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731576"},{"key":"ref27","first-page":"1","article-title":"A 4.5 V-input 0.3-to-1.7 V-output step-down always-dual-path DC–DC converter achieving 91.5%-efficiency with 250 m?-DCR inductor for low-voltage SoCs","author":"ko","year":"2021","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref29","first-page":"2279","article-title":"48 V-to-12 V dual-path hybrid DC–DC converter","author":"hata","year":"2020","journal-title":"Proc IEEE Appl Power Electron Conf Expo (APEC)"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2776298"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162914"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1088\/1674-4926\/41\/11\/112402"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3005795"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2866929"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2015.7231315"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TPEL.2019.2933623"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/10136239\/09927404.pdf?arnumber=9927404","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,6,12]],"date-time":"2023-06-12T18:10:16Z","timestamp":1686593416000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9927404\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,6]]},"references-count":34,"journal-issue":{"issue":"6"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2022.3213835","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,6]]}}}