{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,6,4]],"date-time":"2026-06-04T15:33:23Z","timestamp":1780587203217,"version":"3.54.1"},"reference-count":18,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,4,1]],"date-time":"2023-04-01T00:00:00Z","timestamp":1680307200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2023,4]]},"DOI":"10.1109\/jssc.2022.3230046","type":"journal-article","created":{"date-parts":[[2022,12,28]],"date-time":"2022-12-28T18:42:29Z","timestamp":1672252949000},"page":"1087-1093","source":"Crossref","is-referenced-by-count":15,"title":["Energy-Efficient High Bandwidth 6T SRAM Design on Intel 4 CMOS Technology"],"prefix":"10.1109","volume":"58","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-4051-3789","authenticated-orcid":false,"given":"Yusung","family":"Kim","sequence":"first","affiliation":[{"name":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Clifford","family":"Ong","sequence":"additional","affiliation":[{"name":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Anandkumar Mahadevan","family":"Pillai","sequence":"additional","affiliation":[{"name":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Harish","family":"Jagadeesh","sequence":"additional","affiliation":[{"name":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gwanghyeon","family":"Baek","sequence":"additional","affiliation":[{"name":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Iqbal","family":"Rajwani","sequence":"additional","affiliation":[{"name":"Accelerated Computing Systems and Graphics (AXG), Intel Corporation, Folsom, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8615-9749","authenticated-orcid":false,"given":"Zheng","family":"Guo","sequence":"additional","affiliation":[{"name":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Eric","family":"Karl","sequence":"additional","affiliation":[{"name":"Advanced Design, Technology Development, Intel Corporation, Hillsboro, OR, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2014.6757323"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42614.2022.9731673"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9063049"},{"key":"ref4","first-page":"25","article-title":"The impact of assist-circuit design for 22 nm SRAM and beyond","author":"Karl","year":"2012","journal-title":"IEDM Tech. Dig."},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2016.2607219"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/vlsic.2015.7231282"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/vlsic.2016.7573460"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/vlsit.2018.8510704"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/lssc.2020.3044042"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365988"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2017.7870333"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/vlsicircuits18222.2020.9162815"},{"key":"ref13","first-page":"32","article-title":"Dynamic behavior of SRAM data retention and a novel transient voltage collapse technique for 0.6 V 32 nm LP SRAM","volume-title":"IEDM Tech. Dig.","author":"Wang"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9062967"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2005.864124"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.1989.572629"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/1391469.1391522"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/icicdt.2010.5510252"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/10082904\/09999728.pdf?arnumber=9999728","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,3,14]],"date-time":"2024-03-14T04:50:04Z","timestamp":1710391804000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9999728\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,4]]},"references-count":18,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2022.3230046","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,4]]}}}