{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,4]],"date-time":"2026-03-04T16:39:09Z","timestamp":1772642349774,"version":"3.50.1"},"reference-count":25,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2023,7,1]],"date-time":"2023-07-01T00:00:00Z","timestamp":1688169600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,7,1]],"date-time":"2023-07-01T00:00:00Z","timestamp":1688169600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,7,1]],"date-time":"2023-07-01T00:00:00Z","timestamp":1688169600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100004358","name":"Samsung Electronics Company Ltd","doi-asserted-by":"publisher","award":["IO201210-08000-01"],"award-info":[{"award-number":["IO201210-08000-01"]}],"id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2023,7]]},"DOI":"10.1109\/jssc.2022.3231654","type":"journal-article","created":{"date-parts":[[2022,12,30]],"date-time":"2022-12-30T18:55:38Z","timestamp":1672426538000},"page":"2005-2015","source":"Crossref","is-referenced-by-count":8,"title":["A 25-Gb\/s Single-Ended PAM-4 Receiver With Time-Windowed LSB Decoder for High-Speed Memory Interfaces"],"prefix":"10.1109","volume":"58","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-0594-4206","authenticated-orcid":false,"given":"Yoonjae","family":"Choi","sequence":"first","affiliation":[{"name":"Department of Electrical Engineering, Korea University, Seoul, South Korea"}]},{"given":"Hyunsu","family":"Park","sequence":"additional","affiliation":[{"name":"Department of Semiconductor System Engineering, Korea University, Seoul, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9545-9196","authenticated-orcid":false,"given":"Jonghyuck","family":"Choi","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Korea University, Seoul, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8247-6277","authenticated-orcid":false,"given":"Jincheol","family":"Sim","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Korea University, Seoul, South Korea"}]},{"given":"Youngwook","family":"Kwon","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Korea University, Seoul, South Korea"}]},{"given":"Seungwoo","family":"Park","sequence":"additional","affiliation":[{"name":"Department of Semiconductor System Engineering, Korea University, Seoul, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3695-2703","authenticated-orcid":false,"given":"Seongcheol","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Semiconductor System Engineering, Korea University, Seoul, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-6748-1283","authenticated-orcid":false,"given":"Changmin","family":"Sim","sequence":"additional","affiliation":[{"name":"Department of Semiconductor System Engineering, Korea University, Seoul, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4379-7905","authenticated-orcid":false,"given":"Chulwoo","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Korea University, Seoul, South Korea"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3042240"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3143876"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2705070"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3038818"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365925"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3006864"},{"key":"ref2","first-page":"380","article-title":"A 1.1 V 1y nm 6.4 Gb\/s\/pin 16 Gb DDR5 SDRAM with a phase-rotator-based DLL, high-speed SerDes and RX\/TX equalization scheme","author":"kim","year":"2019","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662509"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2874040"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2875091"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.903076"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3098821"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884342"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2820147"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.826317"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.818567"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.2993064"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3170439"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2717900"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-319-02381-6"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185370"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062937"},{"key":"ref3","first-page":"332","article-title":"An 8.5 Gb\/s\/pin 12 Gb-LPDDR5 SDRAM with a hybrid-bank architecture using skew-tolerant, low-power and speed-boosting techniques in a 2nd generation 10 nm DRAM process","author":"chi","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","first-page":"448","article-title":"A 16 Gb 9.5 Gb\/S\/pin LPDDR5X SDRAM with low-power schemes exploiting dynamic voltage-frequency scaling and offset-calibrated readout sense amplifiers in a fourth generation 10 nm DRAM process","author":"kim","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","first-page":"346","article-title":"A 16 Gb sub-1 V 7.14 Gb\/s\/pin LPDDR5 SDRAM applying a mosaic architecture with a short-feedback 1-tap DFE, an FSS bus with low-level swing and an adaptively controlled body biasing in a 3rd-generation 10 nm DRAM","author":"kim","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/10164681\/10003645.pdf?arnumber=10003645","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,7,17]],"date-time":"2023-07-17T17:41:32Z","timestamp":1689615692000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10003645\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,7]]},"references-count":25,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2022.3231654","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,7]]}}}