{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,25]],"date-time":"2026-04-25T14:34:36Z","timestamp":1777127676747,"version":"3.51.4"},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"8","license":[{"start":{"date-parts":[[2023,8,1]],"date-time":"2023-08-01T00:00:00Z","timestamp":1690848000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,8,1]],"date-time":"2023-08-01T00:00:00Z","timestamp":1690848000000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,8,1]],"date-time":"2023-08-01T00:00:00Z","timestamp":1690848000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,8,1]],"date-time":"2023-08-01T00:00:00Z","timestamp":1690848000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation (SRC) Texas Analog Center of Excellence","doi-asserted-by":"publisher","award":["2810.013"],"award-info":[{"award-number":["2810.013"]}],"id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"NSF","doi-asserted-by":"publisher","award":["1930828"],"award-info":[{"award-number":["1930828"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2023,8]]},"DOI":"10.1109\/jssc.2023.3268238","type":"journal-article","created":{"date-parts":[[2023,5,1]],"date-time":"2023-05-01T18:37:17Z","timestamp":1682966237000},"page":"2300-2313","source":"Crossref","is-referenced-by-count":40,"title":["A 38-GS\/s 7-bit Pipelined-SAR ADC With Speed- Enhanced Bootstrapped Switch and Output Level Shifting Technique in 22-nm FinFET"],"prefix":"10.1109","volume":"58","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7731-4452","authenticated-orcid":false,"given":"Yuanming","family":"Zhu","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0551-8135","authenticated-orcid":false,"given":"Tong","family":"Liu","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2265-0496","authenticated-orcid":false,"given":"Srujan Kumar","family":"Kaile","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3840-6407","authenticated-orcid":false,"given":"Shiva","family":"Kiran","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6505-1138","authenticated-orcid":false,"given":"Il-Min","family":"Yi","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX, USA"}]},{"given":"Ruida","family":"Liu","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8340-4953","authenticated-orcid":false,"given":"Julian Camilo Gomez","family":"Diaz","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-2691-3700","authenticated-orcid":false,"given":"Sebastian","family":"Hoyos","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6555-1474","authenticated-orcid":false,"given":"Samuel","family":"Palermo","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Analog and Mixed Signal Center, Texas A&M University, College Station, TX, USA"}]}],"member":"263","reference":[{"key":"ref13","first-page":"1","article-title":"A 38 GS\/s 7 b time-interleaved pipelined-SAR ADC with speed-enhanced bootstrapped switch in 22 nm FinFET","author":"zhu","year":"2022","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref12","first-page":"474","article-title":"A 10 b 1.5 GS\/s pipelined-SAR ADC with background second-stage common-mode regulation and offset calibration in 14 nm CMOS FinFET","author":"kull","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2015.2474258"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/CICC48029.2020.9075942"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279571"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2884352"},{"key":"ref2","first-page":"114","article-title":"A 1.41 pJ\/b 224 Gb\/s PAM-4 SerDes receiver with 31 dB loss compensation","author":"segal","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2018.2844603"},{"key":"ref17","first-page":"266c","article-title":"112 Gb\/s PAM4 ADC based SERDES receiver for long-reach channels in 10 nm process","author":"krupnik","year":"2019","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1049\/el:19990028"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006312"},{"key":"ref18","doi-asserted-by":"crossref","first-page":"168","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830308","article-title":"An 8-bit 56 GS\/s 64x time-interleaved ADC with bootstrapped sampler and class-AB buffer in 4 nm CMOS","author":"yonar","year":"2022","journal-title":"Proc IEEE Symp VLSI Technol Circuits (VLSI Technol Circuits)"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642204"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2732731"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3012776"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1016\/B978-075067841-4\/50022-1"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2891650"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373420"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2005.851387"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662428"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2017.7993699"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2632300"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2018.8502268"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2859757"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2519397"},{"key":"ref4","first-page":"1","article-title":"A jitter-robust 40 Gb\/s ADC-based multicarrier receiver front end in 22 nm FinFET","author":"zhu","year":"2022","journal-title":"Proc IEEE Custom Integr Circuits Conf (CICC)"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2938414"},{"key":"ref6","first-page":"390","article-title":"A 40 GS\/s 6b ADC in 65 nm CMOS","author":"greshishchev","year":"2010","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3226489"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"https:\/\/ieeexplore.ieee.org\/ielam\/4\/10192489\/10113477-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/10192489\/10113477.pdf?arnumber=10113477","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,8,14]],"date-time":"2023-08-14T17:52:30Z","timestamp":1692035550000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10113477\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,8]]},"references-count":29,"journal-issue":{"issue":"8"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2023.3268238","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,8]]}}}