{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,10,28]],"date-time":"2026-10-28T16:56:27Z","timestamp":1793206587967,"version":"4.5.0"},"reference-count":31,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2023,9,1]],"date-time":"2023-09-01T00:00:00Z","timestamp":1693526400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,9,1]],"date-time":"2023-09-01T00:00:00Z","timestamp":1693526400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,9,1]],"date-time":"2023-09-01T00:00:00Z","timestamp":1693526400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program of China","doi-asserted-by":"publisher","award":["2022YFB4401900"],"award-info":[{"award-number":["2022YFB4401900"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"NSFC","doi-asserted-by":"publisher","award":["62274005"],"award-info":[{"award-number":["62274005"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2023,9]]},"DOI":"10.1109\/jssc.2023.3268719","type":"journal-article","created":{"date-parts":[[2023,5,5]],"date-time":"2023-05-05T13:33:11Z","timestamp":1683293591000},"page":"2564-2574","source":"Crossref","is-referenced-by-count":50,"title":["A Bandwidth-Adaptive Pipelined SAR ADC With Three-Stage Cascoded Floating Inverter Amplifier"],"prefix":"10.1109","volume":"58","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2181-9042","authenticated-orcid":false,"given":"Xiyuan","family":"Tang","sequence":"first","affiliation":[{"name":"Institute for Artificial Intelligence and the School of Integrated Circuits, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8712-2884","authenticated-orcid":false,"given":"Xiangxing","family":"Yang","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9204-3988","authenticated-orcid":false,"given":"Jiaxin","family":"Liu","sequence":"additional","affiliation":[{"name":"Institute of Integrated Circuits and Systems, University of Electronic Science and Technology of China, Chengdu, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Zongnan","family":"Wang","sequence":"additional","affiliation":[{"name":"Institute for Artificial Intelligence and the School of Integrated Circuits, Peking University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9106-1092","authenticated-orcid":false,"given":"Wei","family":"Shi","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5705-2501","authenticated-orcid":false,"given":"David Z.","family":"Pan","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, The University of Texas at Austin, Austin, TX, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Nan","family":"Sun","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2948170"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884231"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2163556"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2004.836230"},{"key":"ref31","author":"murmann","year":"2023","journal-title":"ADC Performance Survey 1997&#x2013;2022"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2006.884231"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2017.8240258"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2042254"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2463094"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2108133"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3038914"},{"key":"ref16","first-page":"200","article-title":"11.4 A 1.5 mW 68 dB SNDR 80 MS\/s 2&#x00D7; interleaved SAR-assisted pipelined ADC in 28 nm CMOS","author":"van der goes","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662319"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2217865"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2960485"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8777942"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063058"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/4.127337"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2943935"},{"key":"ref22","first-page":"376","article-title":"27.4 A 0.4-to-40 MS\/s 75.7 dB-SNDR fully dynamic event-driven pipelined ADC with 3-stage cascoded floating inverter amplifier","author":"tang","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3020194"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2010.2048498"},{"key":"ref27","first-page":"196","article-title":"11.2 A 0.85 fJ\/conversion-step 10b 200 kS\/s subranging SAR ADC in 40 nm CMOS","author":"tai","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2384025"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.1975.1050629"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3015863"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2012.6177096"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/VLSIC.2014.6858451"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2453332"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870469"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2732731"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/10229945\/10119139.pdf?arnumber=10119139","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,9,18]],"date-time":"2023-09-18T13:55:05Z","timestamp":1695045305000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10119139\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,9]]},"references-count":31,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2023.3268719","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,9]]}}}