{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,18]],"date-time":"2026-05-18T17:16:45Z","timestamp":1779124605022,"version":"3.51.4"},"reference-count":21,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100004358","name":"Samsung Electronics Company Ltd., Seoul, South Korea","doi-asserted-by":"publisher","award":["IO201207-07799-01"],"award-info":[{"award-number":["IO201207-07799-01"]}],"id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2023,10]]},"DOI":"10.1109\/jssc.2023.3273238","type":"journal-article","created":{"date-parts":[[2023,5,19]],"date-time":"2023-05-19T17:42:27Z","timestamp":1684518147000},"page":"2931-2945","source":"Crossref","is-referenced-by-count":38,"title":["Neuro-CIM: ADC-Less Neuromorphic Computing-in-Memory Processor With Operation Gating\/Stopping and Digital\u2013Analog Networks"],"prefix":"10.1109","volume":"58","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1783-5296","authenticated-orcid":false,"given":"Sangyeob","family":"Kim","sequence":"first","affiliation":[{"name":"School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6665-9973","authenticated-orcid":false,"given":"Sangjin","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8526-2047","authenticated-orcid":false,"given":"Soyeon","family":"Um","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7049-9191","authenticated-orcid":false,"given":"Soyeon","family":"Kim","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8962-4554","authenticated-orcid":false,"given":"Kwantae","family":"Kim","sequence":"additional","affiliation":[{"name":"Institute of Neuroinformatics, University of Z&#x00FC;rich and ETH Z&#x00FC;rich, Z&#x00FC;rich, Switzerland"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6661-4879","authenticated-orcid":false,"given":"Hoi-Jun","family":"Yoo","sequence":"additional","affiliation":[{"name":"School of Electrical Engineering, Korea Advanced Institute of Science and Technology, Daejeon, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2942367"},{"key":"ref12","article-title":"DIET-SNN: Direct input encoding with leakage and threshold optimization in deep spiking neural networks","author":"rathi","year":"2020","journal-title":"arXiv 2008 03658"},{"key":"ref15","first-page":"255","article-title":"A 4096-neuron 1M-synapse 3.8 PJ\/SOP spiking neural network with on-chip STDP learning and sparse weights in 10 nm FinFET CMOS","author":"chen","year":"2018","journal-title":"Proc IEEE Symp VLSI Circuits"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/BIOCAS.2019.8918995"},{"key":"ref20","first-page":"242","article-title":"A 28 nm SoC with a 1.2 GHz 568 nJ\/prediction sparse deep-neural-network engine with0.1 timing error rate tolerance for IoT applications","author":"whatmough","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR42600.2020.01357"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TPAMI.2021.3114196"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365788"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365958"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492444"},{"key":"ref17","article-title":"Two-step spike encoding scheme and architecture for highly sparse spiking-neural-network","author":"kim","year":"2022","journal-title":"arXiv 2202 03601"},{"key":"ref16","first-page":"30c","article-title":"A 3.43 TOPS\/W 48.9 pJ\/pixel 50.1 nJ\/classification 512 analog neuron sparse coding neural network with on-chip learning and classification in 40 nm CMOS","author":"buhler","year":"2017","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref19","article-title":"A 1-to-4b 16.8-POPS\/W 473-TOPS\/mm2 6T-based in-memory computing SRAM in 22 nm FD-SOI with multi-bit analog batch-normalization","author":"kneip","year":"2022","journal-title":"Proc IEEE European Solid-State Circuits Conf (ESSCIRC)"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC56115.2022.9980595"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.3389\/fnins.2019.00095"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2019.2937440"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2021.3095724"},{"key":"ref4","first-page":"240","article-title":"A 65 nm 3T dynamic analog RAM-based computing-in-memory macro and CNN accelerator with retention enhancement, adaptive analog sparsity and 44 TOPS\/W system energy efficiency","author":"chen","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref3","first-page":"234","article-title":"A 65 nm computing-in-memory-based CNN processor with 2.9-to-35.8 TOPS\/W system energy efficiency using dynamic-sparsity performance-scaling architecture and energy-efficient inter\/intra-macro data reuse","author":"yue","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062985"},{"key":"ref5","first-page":"250","article-title":"A 28 nm 384 kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips","author":"su","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/10262388\/10130013.pdf?arnumber=10130013","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,16]],"date-time":"2023-10-16T18:15:48Z","timestamp":1697480148000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10130013\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10]]},"references-count":21,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2023.3273238","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,10]]}}}