{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T17:50:53Z","timestamp":1774720253160,"version":"3.50.1"},"reference-count":16,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100000038","name":"Natural Sciences and Engineering Research Council of Canada","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100000038","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2023,10]]},"DOI":"10.1109\/jssc.2023.3276262","type":"journal-article","created":{"date-parts":[[2023,5,26]],"date-time":"2023-05-26T17:44:08Z","timestamp":1685123048000},"page":"2907-2918","source":"Crossref","is-referenced-by-count":4,"title":["A Serrodyne Modulator-Based Fractional Frequency Synthesis Technique for Low-Noise, GHz-Rate Clocking"],"prefix":"10.1109","volume":"58","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-2260-7674","authenticated-orcid":false,"given":"Ahmad","family":"Sharkia","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, BC, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8852-1633","authenticated-orcid":false,"given":"Shahriar","family":"Mirabbasi","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, BC, Canada"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0383-1929","authenticated-orcid":false,"given":"Sudip","family":"Shekhar","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, The University of British Columbia, Vancouver, BC, Canada"}]}],"member":"263","reference":[{"key":"ref13","author":"razavi","year":"2012","journal-title":"RF Microelectronics"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/4.341736"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310276"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/4.16303"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2008.920154"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JRPROC.1957.278387"},{"key":"ref2","first-page":"256","article-title":"A 0.01 mm2 4.6-to-5.6 GHz sub-sampling type-I frequency synthesizer with ?254 dB FOM","author":"sharkia","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref1","first-page":"272","article-title":"A 20-to-1000 MHz &#x00B1;14 ps peak-to-peak jitter reconfigurable multi-output all-digital clock generator using open-loop fractional dividers in 65 nm CMOS","author":"elkholy","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2817602"},{"key":"ref8","author":"huang","year":"2008","journal-title":"Direct digital interpolative synthesis"},{"key":"ref7","first-page":"362","article-title":"A 2.3 GHz fractional-N dividerless phase-locked loop with ?112 dBc\/Hz in-band phase noise","author":"huang","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref9","first-page":"1","article-title":"A 9b-linear 14 GHz integrating-mode phase interpolator in 5 nm FinFET process","volume":"65","author":"mishra","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662464"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2874013"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"2200","DOI":"10.1109\/JSSC.2004.836342","article-title":"A quad-band GSM-GPRS transmitter with digital auto-calibration","volume":"39","author":"lee","year":"2004","journal-title":"IEEE J Solid-State Circuits"},{"key":"ref5","first-page":"412","article-title":"A 0.008 mm2 1.5 mW 0.625-to-200 MHz fractional output divider with 120fsrms jitter based on replica-DTC-free background calibration","author":"lin","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/10262388\/10136699.pdf?arnumber=10136699","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,16]],"date-time":"2023-10-16T18:15:44Z","timestamp":1697480144000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10136699\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10]]},"references-count":16,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2023.3276262","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,10]]}}}