{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T16:44:17Z","timestamp":1774716257168,"version":"3.50.1"},"reference-count":29,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"11","license":[{"start":{"date-parts":[[2023,11,1]],"date-time":"2023-11-01T00:00:00Z","timestamp":1698796800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2023,11,1]],"date-time":"2023-11-01T00:00:00Z","timestamp":1698796800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2023,11,1]],"date-time":"2023-11-01T00:00:00Z","timestamp":1698796800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100014188","name":"Commercializations Promotion Agency Outcomes (COMPA) funded by the Ministry of Science and ICT (MSIT), Korea Government","doi-asserted-by":"publisher","award":["2021I100"],"award-info":[{"award-number":["2021I100"]}],"id":[{"id":"10.13039\/501100014188","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Institute of Information & Communications Technology Planning & Evaluation (IITP) funded by the Korea government (MSIT)","award":["2022-0-01171"],"award-info":[{"award-number":["2022-0-01171"]}]},{"DOI":"10.13039\/100004358","name":"Samsung Electronics Co., Ltd","doi-asserted-by":"publisher","award":["I0201211-08055-01"],"award-info":[{"award-number":["I0201211-08055-01"]}],"id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003725","name":"BK21 FOUR project of National Research Foundation (NRF) for the Department of Electrical Engineering, POSTECH","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100003725","name":"National R&D Program through the NRF of Korea funded by the Korea Government","doi-asserted-by":"publisher","award":["2020M3H2A107804514"],"award-info":[{"award-number":["2020M3H2A107804514"]}],"id":[{"id":"10.13039\/501100003725","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2023,11]]},"DOI":"10.1109\/jssc.2023.3287071","type":"journal-article","created":{"date-parts":[[2023,7,3]],"date-time":"2023-07-03T18:12:22Z","timestamp":1688407942000},"page":"3253-3265","source":"Crossref","is-referenced-by-count":5,"title":["A 20-Gb\/s\/Pin Compact Single-Ended DCC-Less DECS Transceiver With CDR-Less RX Front-End for On-Chip Links"],"prefix":"10.1109","volume":"58","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-1742-6713","authenticated-orcid":false,"given":"Jaeyoung","family":"Seo","sequence":"first","affiliation":[{"name":"Samsung Electronics, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-4340-3312","authenticated-orcid":false,"given":"Sooeun","family":"Lee","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-5654-431X","authenticated-orcid":false,"given":"Myungguk","family":"Lee","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Changjae","family":"Moon","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Pohang University of Science and Technology, Pohang, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1528-6235","authenticated-orcid":false,"given":"Byungsub","family":"Kim","sequence":"additional","affiliation":[{"name":"Department of Electrical Engineering, Department of Convergence IT EngineeringDepartment of Semiconductor EngineeringGraduate School of Artificial Intelligence, Pohang University of Science and Technology, Pohang-si, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2279053"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830174"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731763"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2008.931647"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2360379"},{"key":"ref10","first-page":"444","article-title":"A 192-Gb 12-high 896-GB\/s HBM3 DRAM with a TSV auto-calibration scheme and machine-learning-based layout optimization","author":"park","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2962655"},{"key":"ref1","first-page":"276","article-title":"A 1.17 pJ\/b 25 Gb\/s\/pin ground-referenced single-ended serial link for off- and on-package communication in 16 nm CMOS using a process- and temperature-adaptive voltage regulator","author":"wilson","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310289"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2019.2893498"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.3042209"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2020.2969472"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2020.3021865"},{"key":"ref23","first-page":"450","article-title":"A 20 Gb\/s\/pin 1.18 pJ\/b 1149 ?m2 single-ended inverter-based 4-tap addition-only feed-forward equalization transmitter with improved robustness to coefficient errors in 28 nm CMOS","author":"moon","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892189"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2004.93"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2808603"},{"key":"ref22","first-page":"209","article-title":"A 12-Gb\/s AC-coupled FFE TX with adaptive relaxed impedance matching achieving adaptation range of 35–75 Z0 and 30–550 RRX","author":"choi","year":"2018","journal-title":"IEEE Asian Solid-State Circuits Conf (A-SSCC) Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2017.8008547"},{"key":"ref28","first-page":"314","article-title":"A double-tail latch-type voltage sense amplifier with 18 ps Setup+Hold time","author":"schinkel","year":"2007","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2017.8240219"},{"key":"ref29","author":"stephens","year":"2004","journal-title":"Jitter Analysis The Dual-Dirac Model RJ\/DJ and Q-Scale"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2031015"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2596773"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2185184"},{"key":"ref4","first-page":"184","article-title":"A 480 Gb\/s\/mm 1.7 pJ\/b short-reach wireline transceiver using single-ended NRZ for die-to-die applications","author":"mccollough","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3006864"},{"key":"ref6","first-page":"1","article-title":"A 7 nm 0.46 pJ\/bit 20 Gbps with BER 1E-25 die-to-die link using minimum intrinsic auto alignment and noise-immunity encode","author":"hsu","year":"2021","journal-title":"IEEE Symp VLSI Circuits Dig Tech Papers"},{"key":"ref5","first-page":"180","article-title":"A 1.7 pJ\/b 112 Gb\/s XSR transceiver for intra-package communication in 7 nm FinFET technology","author":"yousry","year":"2021","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/10292770\/10171209.pdf?arnumber=10171209","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,11,13]],"date-time":"2023-11-13T19:18:41Z","timestamp":1699903121000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10171209\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,11]]},"references-count":29,"journal-issue":{"issue":"11"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2023.3287071","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2023,11]]}}}