{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,11,27]],"date-time":"2025-11-27T06:45:06Z","timestamp":1764225906177,"version":"3.37.3"},"reference-count":28,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"10","license":[{"start":{"date-parts":[[2023,10,1]],"date-time":"2023-10-01T00:00:00Z","timestamp":1696118400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/creativecommons.org\/licenses\/by-nc-nd\/4.0\/"}],"funder":[{"DOI":"10.13039\/100004358","name":"Samsung Electronics","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2023,10]]},"DOI":"10.1109\/jssc.2023.3294475","type":"journal-article","created":{"date-parts":[[2023,8,14]],"date-time":"2023-08-14T17:52:52Z","timestamp":1692035572000},"page":"2790-2800","source":"Crossref","is-referenced-by-count":3,"title":["A Charge Recycling Logic Data Links for Single- and Multiple-Channel I\/Os"],"prefix":"10.1109","volume":"58","author":[{"given":"Han","family":"Wu","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, National University of Singapore, Queenstown, Singapore"}]},{"given":"Jeong Hoan","family":"Park","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Hwaseong, South Korea"}]},{"given":"Rucheng","family":"Jiang","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, National University of Singapore, Queenstown, Singapore"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3611-4734","authenticated-orcid":false,"given":"Jung-Hwan","family":"Choi","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Hwaseong, South Korea"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3150-1727","authenticated-orcid":false,"given":"Jerald","family":"Yoo","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, National University of Singapore, Queenstown, Singapore"}]}],"member":"263","reference":[{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2007151"},{"key":"ref12","first-page":"442","article-title":"A 0.4-to-1 V 1MHz-to-2 GHz switched-capacitor adiabatic clock driver achieving 55.6% clock power reduction","author":"salem","year":"2017","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783730"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2883725"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2004.1332734"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/PHYCMP.1992.615554"},{"key":"ref2","first-page":"10","article-title":"1.1 computing&#x2019;s energy problem (and what we can do about it)","author":"horowitz","year":"2014","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"journal-title":"Rebooting the IT Revolution A Call to Reaction","year":"2015","key":"ref1"},{"year":"2020","key":"ref17"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC56115.2022.9980680"},{"key":"ref19","first-page":"444","article-title":"A 192-Gb 12-high 896-Gbps HBM3 DRAM with a TSV auto-calibration scheme and machine-learning-based layout optimization","author":"park","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2875092"},{"key":"ref24","first-page":"1","article-title":"A 3.2 Gbps\/pin HBM2E PHY with low power I\/O and enhanced training scheme for 2.5D system-in-package solution","author":"hwang","year":"2020","journal-title":"Proc HOT Chip Symp"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.2991\/amcce-15.2015.306"},{"key":"ref26","first-page":"1","article-title":"A 4 nm 1.15TB\/s HBM3 interface with resistor-tuned offset-calibration and in-situ margin-detection","author":"chae","year":"2023","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIC.2019.8778082"},{"key":"ref20","first-page":"450","article-title":"A 20 Gb\/s\/pin 1.18pJ\/b 1149 ?m2 single-ended inverter-based 4-tap addition-only feed-forward equalization transmitter with improved robustness to coefficient errors in 28 nm CMOS","author":"moon","year":"2022","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref22","first-page":"330","article-title":"A 1.1 V 16GB 640GB\/s HBM2E DRAM with a data-bus window-extension technique and a synergetic on-die ECC scheme","author":"oh","year":"2020","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731740"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062937"},{"key":"ref27","first-page":"96c","article-title":"An 8 nm all-digital 7.3Gb\/s\/pin LPDDR5 PHY with an approximate delay compensation scheme","author":"chael","year":"2019","journal-title":"Proc Symp VLSI Circuits"},{"key":"ref8","first-page":"208","article-title":"A 1.2 V 64Gb 341GB\/S HBM2 stacked DRAM with spiral point-to-point TSV structure and improved bank group data control","author":"cho","year":"2018","journal-title":"IEEE Int Solid-State Circuits Conf (ISSCC) Dig Tech Papers"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2938396"},{"key":"ref9","first-page":"100","article-title":"Driving a capacitive load without dissipating fCV2","author":"svensson","year":"1994","journal-title":"IEEE Symp Low Power Electron Dig Tech Papers"},{"year":"2020","key":"ref4","first-page":"444"},{"year":"2013","key":"ref3","first-page":"95"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2429588"},{"journal-title":"DDR Memory and Interface Design Trends","year":"2011","author":"asakura","key":"ref5"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/10262388\/10215353.pdf?arnumber=10215353","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2023,10,16]],"date-time":"2023-10-16T18:16:09Z","timestamp":1697480169000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10215353\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2023,10]]},"references-count":28,"journal-issue":{"issue":"10"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2023.3294475","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"type":"print","value":"0018-9200"},{"type":"electronic","value":"1558-173X"}],"subject":[],"published":{"date-parts":[[2023,10]]}}}