{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T13:40:50Z","timestamp":1774964450148,"version":"3.50.1"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,1,1]],"date-time":"2024-01-01T00:00:00Z","timestamp":1704067200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2024,1]]},"DOI":"10.1109\/jssc.2023.3319637","type":"journal-article","created":{"date-parts":[[2023,10,11]],"date-time":"2023-10-11T17:46:19Z","timestamp":1697046379000},"page":"184-195","source":"Crossref","is-referenced-by-count":14,"title":["A 4-nm 16-Gb\/s\/pin Single-Ended PAM-4 Parallel Transceiver With Switching-Jitter Compensation and Transmitter Optimization"],"prefix":"10.1109","volume":"59","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7012-9991","authenticated-orcid":false,"given":"Jahoon","family":"Jin","sequence":"first","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Soo-Min","family":"Lee","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5488-1147","authenticated-orcid":false,"given":"Kyunghwan","family":"Min","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sodam","family":"Ju","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jihoon","family":"Lim","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-9314-1855","authenticated-orcid":false,"given":"Jisu","family":"Yook","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-9156-5724","authenticated-orcid":false,"given":"Jihoon","family":"Lee","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Hyunsu","family":"Chae","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0009-0003-0498-7009","authenticated-orcid":false,"given":"Kwonwoo","family":"Kang","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yunji","family":"Hong","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yeongcheol","family":"Jeong","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sung-Sik","family":"Park","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sang-Ho","family":"Kim","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6746-9645","authenticated-orcid":false,"given":"Jongwoo","family":"Lee","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3742-7644","authenticated-orcid":false,"given":"Joonsuk","family":"Kim","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sung Ung","family":"Kwak","sequence":"additional","affiliation":[{"name":"System LSI Business, Samsung Electronics, Gyeonggi, Hwaseong, South Korea"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067738"},{"key":"ref2","volume-title":"Maximum transition avoidance (MTA) encoding","author":"Sudhakaran","year":"2019"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830507"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC53496.2022.9772814"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3104093"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063137"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3042240"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063137"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC56115.2022.9980755"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/A-SSCC53895.2021.9634750"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063081"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9062925"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9062964"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662322"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2019.8662428"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2019.8662523"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662482"},{"key":"ref18","first-page":"480","article-title":"30.4 A 32Gb\/s 2.9pJ\/b transceiver for sequence-coded PAM-4 signalling with 4-to-6dB SNR gain in 28nm FDSOI CMOS","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Dick"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310207"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2018.8310208"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2018.8310210"},{"key":"ref22","first-page":"122","article-title":"6.8 A 100Gb\/s 1.6 Vppd PAM-8 transmitter with high-swing 3+1 hybrid FFE taps in 40nm","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Yang"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3146097"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830421"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2987712"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2039268"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870289"},{"issue":"12","key":"ref28","first-page":"1377","article-title":"A 28 Gb\/s 1.6 pJ\/b PAM-4 transmitter using fractionally spaced 3-tap FFE and Gm-regulated resistive-feedback driver","volume":"64","author":"Ju","year":"2017","journal-title":"IEEE Trans. Circuits Syst. II, Exp. Briefs"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2808603"},{"key":"ref30","first-page":"398","article-title":"23.6 A 0.6 V 4.266Gb\/s\/pin LPDDR4X interface with auto-DQS cleaning and write-VWM training for memory controller","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Lee"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2581815"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2596773"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2875092"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2962655"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3250706"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/10375801\/10278170.pdf?arnumber=10278170","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,10,18]],"date-time":"2024-10-18T17:30:09Z","timestamp":1729272609000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10278170\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,1]]},"references-count":35,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2023.3319637","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,1]]}}}