{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,5,21]],"date-time":"2026-05-21T17:44:41Z","timestamp":1779385481501,"version":"3.53.1"},"reference-count":40,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"9","license":[{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2024,9,1]],"date-time":"2024-09-01T00:00:00Z","timestamp":1725148800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100012166","name":"National Key Research and Development Program","doi-asserted-by":"publisher","award":["2021ZD0114402"],"award-info":[{"award-number":["2021ZD0114402"]}],"id":[{"id":"10.13039\/501100012166","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100002367","name":"Strategic Priority Research Program of Chinese Academy of Sciences","doi-asserted-by":"publisher","award":["XDB44000000"],"award-info":[{"award-number":["XDB44000000"]}],"id":[{"id":"10.13039\/501100002367","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/501100001809","name":"NSFC","doi-asserted-by":"publisher","award":["92267203"],"award-info":[{"award-number":["92267203"]}],"id":[{"id":"10.13039\/501100001809","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2024,9]]},"DOI":"10.1109\/jssc.2024.3377292","type":"journal-article","created":{"date-parts":[[2024,3,28]],"date-time":"2024-03-28T18:59:49Z","timestamp":1711652389000},"page":"3082-3093","source":"Crossref","is-referenced-by-count":4,"title":["A Dynamic Execution Neural Network Processor for Fine-Grained Mixed-Precision Model Training Based on Online Quantization Sensitivity Analysis"],"prefix":"10.1109","volume":"59","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-9873-6574","authenticated-orcid":false,"given":"Ruoyang","family":"Liu","sequence":"first","affiliation":[{"name":"Department of Electronic Engineering, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2683-9835","authenticated-orcid":false,"given":"Chenhan","family":"Wei","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yixiong","family":"Yang","sequence":"additional","affiliation":[{"name":"Nvidia, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Wenxun","family":"Wang","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Binbin","family":"Yuan","sequence":"additional","affiliation":[{"name":"Traffic Control Technology Company Ltd., Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2421-353X","authenticated-orcid":false,"given":"Huazhong","family":"Yang","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4892-2309","authenticated-orcid":false,"given":"Yongpan","family":"Liu","sequence":"additional","affiliation":[{"name":"Department of Electronic Engineering, Tsinghua University, Beijing, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2016.90"},{"key":"ref2","article-title":"YOLOv3: An incremental improvement","author":"Redmon","year":"2018","journal-title":"arXiv:1804.02767"},{"key":"ref3","first-page":"1877","article-title":"Language models are few-shot learners","volume-title":"Proc. Adv. Neural Inf. Process. Syst.","author":"Brown"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR52688.2022.01042"},{"key":"ref5","volume-title":"Trends in the Dollar Training Cost of Machine Learning Systems","author":"Cottier","year":"2023"},{"key":"ref6","first-page":"1","article-title":"A 28 nm 276.55TFLOPS\/W sparse deep-neural-network training processor with implicit redundancy speculation and batch normalization reformulation","volume-title":"Proc. Symp. VLSI Circuits","author":"Wang"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/CICC53496.2022.9772808"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9062989"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830487"},{"key":"ref10","article-title":"On-device training under 256kb memory","author":"Lin","year":"2022","journal-title":"arXiv:2206.15472"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42614.2022.9731762"},{"key":"ref12","first-page":"346","article-title":"A 28 nm 16.9\u2013300TOPS\/W computing-in-memory processor supporting floating-point NN inference\/training with intensive-CIM sparse-digital architecture","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Yue"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067497"},{"key":"ref14","article-title":"DoReFa-Net: Training low bitwidth convolutional neural networks with low bitwidth gradients","author":"Zhou","year":"2016","journal-title":"arXiv:1606.06160"},{"key":"ref15","first-page":"1","article-title":"Hybrid 8-bit floating point (HFP8) training and inference for deep neural networks","volume-title":"Proc. Adv Neural Inf. Process. Syst","volume":"32","author":"Sun"},{"key":"ref16","first-page":"1796","article-title":"Ultra-low precision 4-bit training of deep neural networks","volume-title":"Proc. Adv. Neural Inf. Process. Syst","volume":"33","author":"Sun"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP40776.2020.9054164"},{"key":"ref18","first-page":"1803","article-title":"ActNN: Reducing training memory footprint via 2-bit activation compressed training","volume-title":"Proc. 38th Int. Conf. Mach. Learn.","volume":"139","author":"Chen"},{"key":"ref19","first-page":"1","article-title":"Block-wise dynamic-precision neural network training acceleration via online quantization sensitivity analytics","volume-title":"Proc. 28th Asia South Pacific Design Autom. Conf. (ASP-DAC)","author":"Liu"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365791"},{"key":"ref21","first-page":"1","article-title":"A 40 nm 4.81 TFLOPS\/W 8b floating-point training processor for non-sparse neural networks using shared exponent bias and 24-way fused multiply-add tree","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","volume":"64","author":"Park"},{"key":"ref22","first-page":"1","article-title":"A 3.0 TFLOPS 0.62 V scalable processor core for high compute utilization AI training and inference","volume-title":"Proc. IEEE Symp. VLSI Circuits","author":"Oh"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/CICC48029.2020.9075910"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2019.8662302"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00069"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2865489"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA45697.2020.00086"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3066400"},{"key":"ref29","first-page":"11875","article-title":"HAWQ-V3: Dyadic neural network quantization","volume-title":"Proc. Int. Conf. Mach. Learn.","author":"Yao"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ASP-DAC52403.2022.9712505"},{"key":"ref32","first-page":"1","article-title":"Post training 4-bit quantization of convolutional networks for rapid-deployment","volume-title":"Adv. Neural Inf. Process. Syst.","volume":"32","author":"Banner"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2018.00286"},{"key":"ref34","article-title":"Learning multiple layers of features from tiny images","author":"Krizhevsky","year":"2009"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/CVPR.2009.5206848"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA53966.2022.00067"},{"key":"ref37","volume-title":"TorchVision: PyTorch\u2019s Computer Vision Library","year":"2016"},{"key":"ref38","volume-title":"DDR3 SDRAM Standard","year":"2012"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124545"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731754"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/4\/10648889\/10483251.pdf?arnumber=10483251","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,30]],"date-time":"2024-08-30T10:20:10Z","timestamp":1725013210000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10483251\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2024,9]]},"references-count":40,"journal-issue":{"issue":"9"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2024.3377292","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2024,9]]}}}