{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,7]],"date-time":"2026-04-07T02:01:37Z","timestamp":1775527297207,"version":"3.50.1"},"reference-count":51,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,1,1]],"date-time":"2025-01-01T00:00:00Z","timestamp":1735689600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2025,1]]},"DOI":"10.1109\/jssc.2024.3422826","type":"journal-article","created":{"date-parts":[[2024,8,13]],"date-time":"2024-08-13T13:35:54Z","timestamp":1723556154000},"page":"308-320","source":"Crossref","is-referenced-by-count":18,"title":["PICO-RAM: A PVT-Insensitive Analog Compute-In-Memory SRAM Macro With In Situ Multi-Bit Charge Computing and 6T Thin-Cell-Compatible Layout"],"prefix":"10.1109","volume":"60","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1321-1793","authenticated-orcid":false,"given":"Zhiyu","family":"Chen","sequence":"first","affiliation":[{"name":"Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7081-0725","authenticated-orcid":false,"given":"Ziyuan","family":"Wen","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA"}]},{"given":"Weier","family":"Wan","sequence":"additional","affiliation":[{"name":"Aizip Inc., Cupertino, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0570-4993","authenticated-orcid":false,"given":"Akhil","family":"Reddy Pakala","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-2949-5672","authenticated-orcid":false,"given":"Yiwei","family":"Zou","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA"}]},{"given":"Wei-Chen","family":"Wei","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA"}]},{"given":"Zengyi","family":"Li","sequence":"additional","affiliation":[{"name":"Aizip Inc., Cupertino, CA, USA"}]},{"given":"Yubei","family":"Chen","sequence":"additional","affiliation":[{"name":"Aizip Inc., Cupertino, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7220-9389","authenticated-orcid":false,"given":"Kaiyuan","family":"Yang","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Rice University, Houston, TX, USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757323"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2922889"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731659"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731754"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/vlsitechnologyandcir46769.2022.9830438"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2021.3096236"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067527"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.23919\/vlsitechnologyandcir57934.2023.10185253"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067260"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365766"},{"key":"ref11","first-page":"132","article-title":"A 4 nm 6163-TOPS\/W\/b 4790-TOPS\/mm2\/b SRAM based digital-computing-in-memory macro supporting bit-width flexibility and simultaneous MAC and weight update","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Mori"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3061508"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067305"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731545"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2020.3020286"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9062985"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2018.8310398"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2963616"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.23919\/VLSIT.2019.8776544"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9062995"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2952773"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2642198"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2880918"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2992886"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2987714"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3119018"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/CICC53496.2022.9772826"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3056447"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3080042"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3232601"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067335"},{"key":"ref32","first-page":"250","article-title":"A 28 nm 384 kb 6T-SRAM computation-in-memory macro with 8b precision for AI edge chips","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Su"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2021.3103759"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899730"},{"key":"ref35","first-page":"140","article-title":"A 22 nm delta-sigma computing-in-memory (\u0394\u03a3CIM) SRAM macro with near-zero-mean outputs and LSB-first ADCs achieving 21.38TOPS\/W for 8b-MAC edge AI processing","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Chen"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3199077"},{"key":"ref37","article-title":"PIM-QAT: Neural network quantization for processing-in-memory (PIM) systems","author":"Jin","year":"2022","journal-title":"arXiv:2209.08617"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.23919\/VLSICircuits52068.2021.9492444"},{"key":"ref39","first-page":"2849","article-title":"Fixed point quantization of deep convolutional networks","volume-title":"Proc. Int. Conf. Mach. Learn. (ICML)","author":"Lin"},{"key":"ref40","first-page":"1","article-title":"Fundamental limits on the precision of in-memory architectures","volume-title":"Proc. 39th Int. Conf. Comput.-Aided Design","author":"Gonugondla"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/49.761034"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2020.2992306"},{"key":"ref43","volume-title":"Reshape and Adapt for Output Quantization (RAOQ): Quantization-Aware Training for In-Memory Computing Systems","author":"Zhang","year":"2023"},{"key":"ref44","article-title":"DoReFa-Net: Training low bitwidth convolutional neural networks with low bitwidth gradients","author":"Zhou","year":"2016","journal-title":"arXiv:1606.06160"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/3531437.3539718"},{"key":"ref46","first-page":"134","article-title":"A 28 nm horizontal-weight-shift and vertical-feature-shift-based separate-WL 6T-SRAM computation-in-memory unit-macro for edge depthwise neural-networks","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Wang"},{"key":"ref47","doi-asserted-by":"publisher","DOI":"10.1109\/ICASSP.2019.8683474"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3324954"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3148273"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC59616.2023.10268726"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/CICC57935.2023.10121238"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/4\/10856383\/10634317.pdf?arnumber=10634317","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,9,25]],"date-time":"2025-09-25T17:55:10Z","timestamp":1758822910000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10634317\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,1]]},"references-count":51,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2024.3422826","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,1]]}}}