{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T18:32:07Z","timestamp":1782930727544,"version":"3.54.5"},"reference-count":35,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T00:00:00Z","timestamp":1738368000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T00:00:00Z","timestamp":1738368000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,2,1]],"date-time":"2025-02-01T00:00:00Z","timestamp":1738368000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/100004358","name":"Samsung","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100004358","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2025,2]]},"DOI":"10.1109\/jssc.2024.3432096","type":"journal-article","created":{"date-parts":[[2024,8,1]],"date-time":"2024-08-01T14:04:50Z","timestamp":1722521090000},"page":"497-508","source":"Crossref","is-referenced-by-count":4,"title":["A 12.24-GHz MDLL With a 102-Multiplication Factor Using a Power-Gating-Based Ring Oscillator"],"prefix":"10.1109","volume":"60","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6832-7929","authenticated-orcid":false,"given":"Yoonseo","family":"Cho","sequence":"first","affiliation":[{"name":"School of Electrical Engineering, Korea Advanced Institute of Science and Technology (KAIST), Daejeon, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Jeonghyun","family":"Lee","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Hwaseong, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5399-1782","authenticated-orcid":false,"given":"Suneui","family":"Park","sequence":"additional","affiliation":[{"name":"Samsung Electronics, Hwaseong, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1785-2376","authenticated-orcid":false,"given":"Seyeon","family":"Yoo","sequence":"additional","affiliation":[{"name":"Qualcomm Inc., San Diego, CA, USA"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3055-8684","authenticated-orcid":false,"given":"Jaehyouk","family":"Choi","sequence":"additional","affiliation":[{"name":"Department of Electrical and Computer Engineering, Seoul National University (SNU), Seoul, South Korea"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2018.8310336"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2936765"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2019.8662494"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2018.8310342"},{"issue":"1","key":"ref5","first-page":"1","article-title":"A 7\u20138.5 GHz LC voltage-controlled oscillator with\u2013111.7 dBc\/Hz phase noise at 1-MHz offset for ultra-low-jitter phase-locked loop","volume":"9","author":"Jo","year":"2023","journal-title":"IDEC J. Integr. Circuits Syst."},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2908753"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2995326"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2017.7870306"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2872539"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42614.2022.9731714"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2904884"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3210212"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2013.2254552"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2014.6757469"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2941259"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2734910"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2870551"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3021279"},{"key":"ref19","first-page":"1","article-title":"A 122fsrms-jitter and -60 dBc-reference-spur 12.24 GHz MDLL with a 102\u2014Multiplication factor using a power-gating technique","volume-title":"Proc. IEEE Symp. VLSI Technol. Circuits (VLSI Technol. Circuits)","author":"Cho"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3123156"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3087512"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2015.2447001"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3321837"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.2993064"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3200475"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2013.2268514"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3028376"},{"issue":"4","key":"ref28","first-page":"37","article-title":"A low-jitter ring-DCO-based digital PLL using P\/I-gain co-optimization and optimally spaced TDC for flicker-noise reduction","volume":"9","author":"Hwang","year":"2023","journal-title":"IDEC J. Integr. Circuits Syst."},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.914283"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2008.2006225"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2021.3049365"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2009.2032470"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2017.2679683"},{"key":"ref34","first-page":"214","article-title":"A 0.021 mm2 65 nm CMOS 2.5 GHz digital injection-locked clock multiplier with injection pulse shaping achieving -79 dBc reference spur and 0.496 mW\/GHz power efficiency","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Xu"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3320886"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/4\/10857664\/10620066.pdf?arnumber=10620066","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,2]],"date-time":"2025-12-02T18:48:16Z","timestamp":1764701296000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10620066\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,2]]},"references-count":35,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2024.3432096","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,2]]}}}