{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,28]],"date-time":"2026-03-28T17:50:54Z","timestamp":1774720254965,"version":"3.50.1"},"reference-count":27,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"5","license":[{"start":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T00:00:00Z","timestamp":1746057600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T00:00:00Z","timestamp":1746057600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,5,1]],"date-time":"2025-05-01T00:00:00Z","timestamp":1746057600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"ItoM"},{"name":"Holland High Tech in a public-privatecooperation for research and development in the High Tech Systems and Materials Top Sector"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2025,5]]},"DOI":"10.1109\/jssc.2024.3464236","type":"journal-article","created":{"date-parts":[[2024,10,4]],"date-time":"2024-10-04T13:36:05Z","timestamp":1728048965000},"page":"1694-1707","source":"Crossref","is-referenced-by-count":3,"title":["A Dual-Alternating-Slope Digital-to-Time Converter Leveraging Mismatch to Improve Delay Step Size"],"prefix":"10.1109","volume":"60","author":[{"ORCID":"https:\/\/orcid.org\/0009-0009-7367-1781","authenticated-orcid":false,"given":"Nimit","family":"Jain","sequence":"first","affiliation":[{"name":"IC-Design Group, Faculty of Electrical Engineering, Mathematics and Computer Science, University of Twente, Enschede, AE, The Netherlands"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2487-8996","authenticated-orcid":false,"given":"Eric A. M.","family":"Klumperink","sequence":"additional","affiliation":[{"name":"IC-Design Group, Faculty of Electrical Engineering, Mathematics and Computer Science, University of Twente, Enschede, AE, The Netherlands"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Harm van","family":"Rumpt","sequence":"additional","affiliation":[{"name":"resides in 5232, ’s-Hertogenbosch, The Netherlands"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6790-5873","authenticated-orcid":false,"given":"Bram","family":"Nauta","sequence":"additional","affiliation":[{"name":"IC-Design Group, Faculty of Electrical Engineering, Mathematics and Computer Science, University of Twente, Enschede, AE, The Netherlands"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2011.5746216"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2011.2162917"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2015.2414421"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2878836"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2817602"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2899726"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2936967"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3019344"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42613.2021.9365821"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3106514"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/CICC53496.2022.9772842"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067511"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/LSSC.2023.3254521"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067785"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3311681"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/cicc.2018.8357042"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/esscirc.2014.6942026"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2939663"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.23919\/vlsicircuits52068.2021.9492452"},{"key":"ref20","volume-title":"Dual slope digital-to-time converter and methods for calibrating the same","author":"Mukherjee","year":"2023"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2021.3105451"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2015.2433512"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2008.918972"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2023.3323429"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2016.2592620"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/RFIC54546.2022.9863080"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2987731"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/4\/10976259\/10705095.pdf?arnumber=10705095","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,2]],"date-time":"2025-12-02T18:48:20Z","timestamp":1764701300000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10705095\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,5]]},"references-count":27,"journal-issue":{"issue":"5"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2024.3464236","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,5]]}}}