{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,18]],"date-time":"2026-03-18T14:23:35Z","timestamp":1773843815807,"version":"3.50.1"},"reference-count":68,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"European High Performance Computing Joint Undertaking (JU) under Framework Partnership Agreement","award":["800928"],"award-info":[{"award-number":["800928"]}]},{"name":"Specific Grant Agreement","award":["101036168 (EPI SGA2)"],"award-info":[{"award-number":["101036168 (EPI SGA2)"]}]},{"name":"Specific Grant Agreement","award":["101034126 (The EU Pilot)"],"award-info":[{"award-number":["101034126 (The EU Pilot)"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2025,4]]},"DOI":"10.1109\/jssc.2025.3529249","type":"journal-article","created":{"date-parts":[[2025,1,30]],"date-time":"2025-01-30T19:18:26Z","timestamp":1738264706000},"page":"1324-1338","source":"Crossref","is-referenced-by-count":6,"title":["Occamy: A 432-Core Dual-Chiplet Dual-HBM2E 768-DP-GFLOP\/s RISC-V System for 8-to-64-bit Dense and Sparse Computing in 12-nm FinFET"],"prefix":"10.1109","volume":"60","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4230-1381","authenticated-orcid":false,"given":"Paul","family":"Scheffler","sequence":"first","affiliation":[{"name":"Integrated Systems Laboratory (IIS), ETH Zurich, Zürich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0326-9676","authenticated-orcid":false,"given":"Thomas","family":"Benz","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory (IIS), ETH Zurich, Zürich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0009-0004-9412-6081","authenticated-orcid":false,"given":"Viviane","family":"Potocnik","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory (IIS), ETH Zurich, Zürich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0009-0007-9700-1286","authenticated-orcid":false,"given":"Tim","family":"Fischer","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory (IIS), ETH Zurich, Zürich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-7986-1975","authenticated-orcid":false,"given":"Luca","family":"Colagrande","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory (IIS), ETH Zurich, Zürich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8683-8060","authenticated-orcid":false,"given":"Nils","family":"Wistoff","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory (IIS), ETH Zurich, Zürich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0009-0008-7508-599X","authenticated-orcid":false,"given":"Yichao","family":"Zhang","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory (IIS), ETH Zurich, Zürich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-3011-6368","authenticated-orcid":false,"given":"Luca","family":"Bertaccini","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory (IIS), ETH Zurich, Zürich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0041-7917","authenticated-orcid":false,"given":"Gianmarco","family":"Ottavi","sequence":"additional","affiliation":[{"name":"Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Bologna, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8395-7585","authenticated-orcid":false,"given":"Manuel","family":"Eggimann","sequence":"additional","affiliation":[{"name":"Axelera AI, Zurich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9199-1708","authenticated-orcid":false,"given":"Matheus","family":"Cavalcante","sequence":"additional","affiliation":[{"name":"Robust Systems Group (RSG), Computer Systems Laboratory (CSL), Stanford University, Stanford, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1310-0911","authenticated-orcid":false,"given":"Gianna","family":"Paulin","sequence":"additional","affiliation":[{"name":"Robust Systems Group (RSG), Computer Systems Laboratory (CSL), Stanford University, Stanford, CA, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8476-554X","authenticated-orcid":false,"given":"Frank K.","family":"G\u00fcrkaynak","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory (IIS), ETH Zurich, Zürich, Switzerland"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0651-5393","authenticated-orcid":false,"given":"Davide","family":"Rossi","sequence":"additional","affiliation":[{"name":"Department of Electrical, Electronic and Information Engineering (DEI), University of Bologna, Bologna, Italy"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8068-3806","authenticated-orcid":false,"given":"Luca","family":"Benini","sequence":"additional","affiliation":[{"name":"Integrated Systems Laboratory (IIS), ETH Zurich, Zürich, Switzerland"}]}],"member":"263","reference":[{"issue":"1","key":"ref1","first-page":"10882","article-title":"Sparsity in deep learning: Pruning and growth for efficient inference and training in neural networks","volume":"22","author":"Hoefler","year":"2021","journal-title":"J. Mach. Learn. Res."},{"key":"ref2","article-title":"SpQR: A sparse-quantized representation for near-lossless LLM weight compression","volume-title":"Proc. 12th Int. Conf. Learn. Represent.","author":"Dettmers"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.14778\/3626292.3626303"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ACCESS.2015.2430359"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/3524059.3532370"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1007\/s42979-024-02958-3"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2021.3078153"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1177\/10943420211065723"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/3577193.3593716"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2022.3223512"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/PMBS51919.2020.00006"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/IPDPS49936.2021.00016"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3391665"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3324954"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3386878"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3043870"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO50266.2020.00068"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2018.00067"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2960480"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358330"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358275"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358276"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631383"},{"key":"ref24","first-page":"1332","article-title":"A tensor marshaling unit for sparse tensor algebra on general-purpose processors","volume-title":"Proc. 56th Annu. IEEE\/ACM Int. Symp. Microarchitecture","author":"Siracusa"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00025"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/3352460.3358269"},{"key":"ref27","first-page":"736","article-title":"Stream-based memory access specialization for general purpose processors","volume-title":"Proc. ACM\/IEEE 46th Annu. Int. Symp. Comput. Archit. (ISCA)","author":"Wang"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA52012.2021.00088"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/3503222.3507705"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/TETC.2024.3365354"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2023.3322029"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2023.3329930"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46783.2024.10631529"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2020.3027900"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063103"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/3649329.3658494"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI54635.2022.00021"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2049662.2049663"},{"key":"ref39","article-title":"Semi-supervised classification with graph convolutional networks","volume-title":"Proc. 5th Int. Conf. Learn. Represent.","author":"Kipf"},{"key":"ref40","article-title":"Benchmarking graph neural networks","volume":"24","author":"Dwivedi","year":"2020","journal-title":"J. Mach. Learn. Res."},{"key":"ref41","first-page":"496","article-title":"Link-based classification","volume-title":"Proc. 20th Int. Conf. Mach. Learn. (ICML)","author":"Lu"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1609\/aimag.v29i3.2157"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/TCASAI.2024.3459412"},{"key":"ref44","article-title":"FlashAttention-2: Faster attention with better parallelism and work partitioning","volume-title":"Proc. 12th Int. Conf. Learn. Represent.","author":"Dao"},{"key":"ref45","doi-asserted-by":"publisher","DOI":"10.1145\/3357375"},{"key":"ref46","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3118046"},{"key":"ref47","volume-title":"SG2042 Technical Reference Manual","author":"Wei","year":"2023"},{"key":"ref48","doi-asserted-by":"publisher","DOI":"10.1109\/HCS49909.2020.9220630"},{"key":"ref49","doi-asserted-by":"publisher","DOI":"10.1109\/HOTCHIPS.2019.8875673"},{"key":"ref50","doi-asserted-by":"publisher","DOI":"10.1109\/Cluster48925.2021.00106"},{"key":"ref51","doi-asserted-by":"publisher","DOI":"10.1109\/HCS55958.2022.9895592"},{"key":"ref52","volume-title":"NVIDIA H100 Tensor Core GPU Architecture","year":"2024"},{"key":"ref53","doi-asserted-by":"publisher","DOI":"10.1145\/3627535.3638476"},{"key":"ref54","volume-title":"NVIDIA A100 Tensor Core GPU Architecture","year":"2020"},{"key":"ref55","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC19947.2020.9063113"},{"key":"ref56","first-page":"38","article-title":"2.1 Zen 2: The AMD 7nm energy-efficient highperformance","volume":"66","author":"Munger","year":"2023","journal-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers"},{"key":"ref57","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2024.3375070"},{"key":"ref58","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731627"},{"key":"ref59","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365803"},{"key":"ref60","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42614.2022.9731107"},{"key":"ref61","doi-asserted-by":"publisher","DOI":"10.1109\/HCS52781.2021.9566865"},{"key":"ref62","volume-title":"App Metrics for Intel Microprocessors","year":"2024"},{"key":"ref63","volume-title":"Architecture Day 2021","year":"2021"},{"key":"ref64","first-page":"1","article-title":"Hwacha: A D Rallel RISC-V extension and implementation","volume-title":"Proc. Inaugural RISC-V Summit","author":"Schmidt"},{"key":"ref65","volume-title":"High Performance Computing Tuning Guide for AMD EPYC 9004 Series Processors","year":"2024"},{"key":"ref66","volume-title":"Green500 List","author":"Strohmaier","year":"2024"},{"key":"ref67","volume-title":"Top500 List","author":"Strohmaier","year":"2024"},{"key":"ref68","volume-title":"Australia Launches Virga Cluster With Dell AI Rackservers for Health Research","author":"Mellor","year":"2024"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/4\/10944491\/10858367.pdf?arnumber=10858367","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,3,29]],"date-time":"2025-03-29T03:33:21Z","timestamp":1743219201000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10858367\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4]]},"references-count":68,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2025.3529249","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,4]]}}}