{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,26]],"date-time":"2026-02-26T15:25:19Z","timestamp":1772119519583,"version":"3.50.1"},"reference-count":34,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"4","license":[{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2025,4,1]],"date-time":"2025-04-01T00:00:00Z","timestamp":1743465600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2025,4]]},"DOI":"10.1109\/jssc.2025.3541573","type":"journal-article","created":{"date-parts":[[2025,2,27]],"date-time":"2025-02-27T13:49:13Z","timestamp":1740664153000},"page":"1349-1358","source":"Crossref","is-referenced-by-count":3,"title":["A 4.7-to-5.3-Gb\/s Fault-Injection and Side-Channel Attack-Resistant AES-256 Engine Using Masked Isomorphic Composite Fields in Intel 4 CMOS"],"prefix":"10.1109","volume":"60","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7399-1886","authenticated-orcid":false,"given":"Raghavan","family":"Kumar","sequence":"first","affiliation":[{"name":"Intel Labs, Intel Corporation, Hillsboro, OR, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4590-7875","authenticated-orcid":false,"given":"Sachin","family":"Taneja","sequence":"additional","affiliation":[{"name":"Intel Labs, Intel Corporation, Hillsboro, OR, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5207-1079","authenticated-orcid":false,"given":"Vivek","family":"De","sequence":"additional","affiliation":[{"name":"Intel Labs, Intel Corporation, Hillsboro, OR, USA"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1344-7533","authenticated-orcid":false,"given":"Sanu K.","family":"Mathew","sequence":"additional","affiliation":[{"name":"Intel Labs, Intel Corporation, Hillsboro, OR, USA"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1007\/3-540-48405-1_25"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2034081"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2869142"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/SP40000.2020.00057"},{"key":"ref5","first-page":"1","article-title":"A testing methodology for side-channel resistance validation","volume-title":"Proc. NIST Non-Invasive Attack Test. Workshop","author":"Goodwill"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"446","DOI":"10.1007\/978-3-540-68914-0_27","article-title":"A very compact \u2019perfectly masked\u2019 Sbox for AES","volume-title":"Applied Cryptography and Network Security","author":"Canright","year":"2008"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30564-4_5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42614.2022.9731739"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3230372"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/jssc.2019.2960482"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2822691"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3032975"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3052146"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42613.2021.9365978"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.1965.4323904"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2019.8741030"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1007\/s13389-021-00259-6"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/vlsitechnologyandcir46769.2022.9830157"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/GCCE.2016.7800490"},{"key":"ref20","first-page":"224","article-title":"Differential fault analysis of the advanced encryption standard using a single fault","volume-title":"Proc. WISTP","volume":"6633","author":"Tunstall"},{"key":"ref21","first-page":"293","article-title":"Differential fault analysis on AES","volume-title":"Applied Cryptography and Network Security","volume":"306","author":"Dusart"},{"key":"ref22","first-page":"513","article-title":"Differential fault analysis of secret key cryptosystems","volume-title":"Advances in Cryptology","volume":"1294","author":"Biham","year":"1997"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2011.5746316"},{"key":"ref24","first-page":"100","article-title":"High-performance concurrent error detection scheme for AES hardware","volume-title":"Cryptographic Hardware and Embedded Systems (CHES)","volume":"5154","author":"Satoh","year":"2008"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2031651"},{"key":"ref26","first-page":"1","article-title":"A 100 Gbps fault-injection attack resistant AES-256 engine with 99.1-to-99.99% error coverage in Intel 4 CMOS","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Kumar"},{"key":"ref27","doi-asserted-by":"crossref","first-page":"27","DOI":"10.1007\/978-3-319-49445-6_2","article-title":"Cheap and cheerful: A low-cost digital sensor for detecting laser fault injection attacks","volume-title":"Security, Privacy, and Applied Cryptography Engineering (SPACE)","volume":"10076","author":"He","year":"2016"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/HST.2014.6855563"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/FDTC.2009.40"},{"key":"ref30","first-page":"304","article-title":"A synthesizable design-agnostic timing fault injection monitor covering 2 MHz to 1.26 GHz clocks in 65 nm CMOS","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","volume":"67","author":"He"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/VLSITechnologyandCir46769.2022.9830194"},{"key":"ref32","first-page":"1","article-title":"A 4.7-to-5.3 Gbps fault-injection attack resistant AES-256 engine using isomorphic composite fields in Intel 4 CMOS","volume-title":"Proc. IEEE Symp. VLSI Technol. Circuits (VLSI Technol. Circuits)","author":"Kumar"},{"issue":"4","key":"ref33","doi-asserted-by":"crossref","first-page":"767","DOI":"10.1109\/JSSC.2011.2108131","article-title":"53 Gbps native GF(24)2 composite-field AES-encrypt\/decrypt accelerator for content-protection in 45 nm high-performance microprocessors","volume":"46","author":"Mathew","year":"2011","journal-title":"IEEE J. Solid-State Circuits"},{"key":"ref34","doi-asserted-by":"crossref","first-page":"302","DOI":"10.1007\/978-981-99-8730-6_10","article-title":"Quantitative fault injection analysis","volume-title":"Advances in Cryptology\u2014ASIACRYPT 2023","author":"Feldtkeller","year":"2023"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/4\/10944491\/10907922.pdf?arnumber=10907922","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,12,2]],"date-time":"2025-12-02T18:48:23Z","timestamp":1764701303000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/10907922\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2025,4]]},"references-count":34,"journal-issue":{"issue":"4"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2025.3541573","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2025,4]]}}}