{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,13]],"date-time":"2026-07-13T21:05:49Z","timestamp":1783976749362,"version":"3.55.0"},"reference-count":44,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100018537","name":"New Generation Artificial Intelligence-National Science and Technology Major Project, China","doi-asserted-by":"publisher","award":["2025ZD0122504"],"award-info":[{"award-number":["2025ZD0122504"]}],"id":[{"id":"10.13039\/501100018537","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Science and Technology Development Fund (FDCT), Macao, SAR","award":["0010\/2023\/RIA1"],"award-info":[{"award-number":["0010\/2023\/RIA1"]}]},{"name":"Science and Technology Development Fund (FDCT), Macao, SAR","award":["0038\/2025\/RIB1"],"award-info":[{"award-number":["0038\/2025\/RIB1"]}]},{"name":"Science and Technology Development Fund (FDCT), Macao, SAR","award":["001\/2025\/NRP"],"award-info":[{"award-number":["001\/2025\/NRP"]}]},{"DOI":"10.13039\/501100005195","name":"University of Macau","doi-asserted-by":"publisher","award":["MYRG-GRG2024-00118-IME"],"award-info":[{"award-number":["MYRG-GRG2024-00118-IME"]}],"id":[{"id":"10.13039\/501100005195","id-type":"DOI","asserted-by":"publisher"}]},{"name":"Nanjing Science and Technology Planning Project","award":["202401015"],"award-info":[{"award-number":["202401015"]}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2026,7]]},"DOI":"10.1109\/jssc.2026.3671779","type":"journal-article","created":{"date-parts":[[2026,3,30]],"date-time":"2026-03-30T20:07:01Z","timestamp":1774901221000},"page":"3154-3168","source":"Crossref","is-referenced-by-count":0,"title":["A 12-bit 1-GS\/s Single-Channel Pipelined ADC With Open-Loop Floating Inverter Amplifier and Residue-Dependent Integration Time Compensation"],"prefix":"10.1109","volume":"61","author":[{"ORCID":"https:\/\/orcid.org\/0009-0002-7126-2836","authenticated-orcid":false,"given":"Hongjiang","family":"Chen","sequence":"first","affiliation":[{"name":"Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Yuhang","family":"Peng","sequence":"additional","affiliation":[{"name":"Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-9512-4529","authenticated-orcid":false,"given":"Liang","family":"Qi","sequence":"additional","affiliation":[{"name":"Department of Micro\/Nano Electronics, Shanghai Jiao Tong University, Shanghai, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-8613-8689","authenticated-orcid":false,"given":"Biao","family":"Wang","sequence":"additional","affiliation":[{"name":"Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9346-8291","authenticated-orcid":false,"given":"Sai-Weng","family":"Sin","sequence":"additional","affiliation":[{"name":"Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-2821-648X","authenticated-orcid":false,"given":"Rui P.","family":"Martins","sequence":"additional","affiliation":[{"name":"Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-9279-9603","authenticated-orcid":false,"given":"Mingqiang","family":"Guo","sequence":"additional","affiliation":[{"name":"Department of ECE, State-Key Laboratory of Analog and Mixed-Signal VLSI, Institute of Microelectronics, and the Faculty of Science and Technology, University of Macau, Macau, China"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/COMST.2020.3012715"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2015.2452372"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067475"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42615.2023.10067258"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2879923"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2021.3053893"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49661.2025.10904766"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/isscc.2019.8662524"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2024.3496490"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2732731"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2017.2778277"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3235521"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC49657.2024.10454297"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2020.2966276"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3018164"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2009.2032637"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2007.892154"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2003.819167"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.3023882"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1109\/ESSERC66193.2025.11214111"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2815654"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/isscc19947.2020.9062895"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/ASSCC.2016.7844136"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2987684"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TIM.2007.907950"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TCSI.2022.3169508"},{"key":"ref27","volume-title":"Analysis and Design of Analog Integrated Circuits","author":"Gray","year":"2017"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2938450"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3231783"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2020.2987699"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067687"},{"key":"ref32","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3171790"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2960485"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2007.373420"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2018.2820147"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937491"},{"key":"ref37","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2017.7870368"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3268719"},{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3290119"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC42615.2023.10067822"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1109\/isscc42614.2022.9731625"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/cicc63670.2025.10982772"},{"key":"ref43","doi-asserted-by":"publisher","DOI":"10.1109\/tcsi.2017.2679748"},{"key":"ref44","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2024.3412090"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/4\/11589468\/11458092.pdf?arnumber=11458092","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,7,13]],"date-time":"2026-07-13T20:04:24Z","timestamp":1783973064000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11458092\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,7]]},"references-count":44,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2026.3671779","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,7]]}}}