{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T20:39:42Z","timestamp":1782938382431,"version":"3.54.5"},"reference-count":42,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"7","license":[{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T00:00:00Z","timestamp":1782864000000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE J. Solid-State Circuits"],"published-print":{"date-parts":[[2026,7]]},"DOI":"10.1109\/jssc.2026.3693894","type":"journal-article","created":{"date-parts":[[2026,5,22]],"date-time":"2026-05-22T19:36:19Z","timestamp":1779478579000},"page":"3193-3207","source":"Crossref","is-referenced-by-count":0,"title":["A 28-nm FD-SOI CMOS Analog-IMC Core Based on PCM Featuring 8 512 \u00d7 512-Weight Layers and 28M Weights\u00d7TOPs\/W\/mm\n                    <sup>2<\/sup>"],"prefix":"10.1109","volume":"61","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-4988-9982","authenticated-orcid":false,"given":"Marco","family":"Pasotti","sequence":"first","affiliation":[{"name":"STMicroelectronics, Agrate Brianza, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4315-1269","authenticated-orcid":false,"given":"Riccardo","family":"Zurla","sequence":"additional","affiliation":[{"name":"STMicroelectronics, Pavia, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"J. J. Bertolini","family":"Agnoletto","sequence":"additional","affiliation":[{"name":"STMicroelectronics, Agrate Brianza, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0009-5271-3938","authenticated-orcid":false,"given":"Emanuela","family":"Calvetti","sequence":"additional","affiliation":[{"name":"STMicroelectronics, Agrate Brianza, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0952-3839","authenticated-orcid":false,"given":"Alessio","family":"Antolini","sequence":"additional","affiliation":[{"name":"ARCES-DEI, University of Bologna, Bologna, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5267-2421","authenticated-orcid":false,"given":"Andrea","family":"Lico","sequence":"additional","affiliation":[{"name":"ARCES-DEI, University of Bologna, Bologna, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Giuseppe","family":"Desoli","sequence":"additional","affiliation":[{"name":"STMicroelectronics, Agrate Brianza, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0009-0006-6994-4503","authenticated-orcid":false,"given":"Riccardo","family":"Vignali","sequence":"additional","affiliation":[{"name":"Department of Electrical, Computer, and Biomedical Engineering, University of Pavia, Pavia, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Luca","family":"Iannelli","sequence":"additional","affiliation":[{"name":"Department of Electrical, Computer, and Biomedical Engineering, University of Pavia, Pavia, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-5400-1429","authenticated-orcid":false,"given":"Luigi","family":"Croce","sequence":"additional","affiliation":[{"name":"STMicroelectronics, Agrate Brianza, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-0103-8126","authenticated-orcid":false,"given":"Francesco","family":"Zavalloni","sequence":"additional","affiliation":[{"name":"ARCES-DEI, University of Bologna, Bologna, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0001-6994-2088","authenticated-orcid":false,"given":"Eleonora Franchi","family":"Scarselli","sequence":"additional","affiliation":[{"name":"ARCES-DEI, University of Bologna, Bologna, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-1862-2409","authenticated-orcid":false,"given":"Alessandro","family":"Cabrini","sequence":"additional","affiliation":[{"name":"Department of Electrical, Computer, and Biomedical Engineering, University of Pavia, Pavia, Italy"}],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD51958.2021.9643488"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MSSC.2019.2922889"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ASICON52560.2021.9620412"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2022.3170152"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2019.2963616"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2023.3269098"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/3502721"},{"key":"ref8","volume-title":"Deep Learning","author":"Goodfellow","year":"2016"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ESSCIRC53450.2021.9567817"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1073\/pnas.1815682116"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-031-26066-7_6"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/JXCDC.2023.3265803"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TNNLS.2017.2778940"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-020-1942-4"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1116\/1.3301579"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/JETCAS.2016.2547718"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5937569"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1002\/aisy.202000040"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2022.3140414"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.23919\/vlsicircuits52068.2021.9492362"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1038\/s41586-023-06337-5"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2022.3233292"},{"key":"ref23","first-page":"18.4.1","article-title":"Truly innovative 28 nm FDSOI technology for automotive micro-controller applications embedding 16 MB phase change memory","author":"Arnaud","year":"2018","journal-title":"IEDM Tech. Dig."},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1109\/OJSSCS.2024.3432468"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2024.3480898"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM19574.2021.9720519"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM50854.2024.10873479"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/esserc66193.2025.11214112"},{"key":"ref29","volume-title":"Design of Analog CMOS Integrated Circuits","author":"Razavi","year":"2001"},{"key":"ref30","volume-title":"Analysis and Design of Analog Integrated Circuits","author":"Gray","year":"2001"},{"key":"ref31","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2009.2016204"},{"key":"ref32","volume-title":"ADC Performance Survey 1997\u20132025","author":"Murmann","year":"2025"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1109\/TCSII.2026.3661725"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1109\/isscc49657.2024.10454468"},{"key":"ref35","first-page":"566","article-title":"34.1 A 28 nm 83.23 TFLOPS\/W POSIT-based compute-in-memory macro for high-accuracy AI applications","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Wang"},{"key":"ref36","first-page":"500","article-title":"33.4 A 28 nm 2 Mb STT-MRAM computing-in-memory macro with a refined bit-cell and 22.4\u201341.5TOPS\/W for AI inference","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Cai"},{"key":"ref37","first-page":"518","article-title":"A 28 nm 106.85 TOPS\/W and 77.68 TFLOPS\/W CIM macro with stage-wise-enabled lossless compressors based on sign-bit-embedded transition-counting-lines for edge-AI devices","volume-title":"IEEE Int. Solid-State Circuits Conf. (ISSCC) Dig. Tech. Papers","author":"Feng"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1109\/ESSERC66193.2025.11214085"},{"key":"ref39","volume-title":"MATLAB Deep Learn. Toolbox","year":"2024"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-020-16108-9"},{"key":"ref41","doi-asserted-by":"publisher","DOI":"10.1038\/s41467-024-51221-z"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1038\/s41928-023-01010-1"}],"container-title":["IEEE Journal of Solid-State Circuits"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/4\/11589468\/11534505.pdf?arnumber=11534505","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,7,1]],"date-time":"2026-07-01T19:36:35Z","timestamp":1782934595000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11534505\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,7]]},"references-count":42,"journal-issue":{"issue":"7"},"URL":"https:\/\/doi.org\/10.1109\/jssc.2026.3693894","relation":{},"ISSN":["0018-9200","1558-173X"],"issn-type":[{"value":"0018-9200","type":"print"},{"value":"1558-173X","type":"electronic"}],"subject":[],"published":{"date-parts":[[2026,7]]}}}