{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T08:19:34Z","timestamp":1725783574653},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/lascas.2014.6820272","type":"proceedings-article","created":{"date-parts":[[2014,5,30]],"date-time":"2014-05-30T18:59:56Z","timestamp":1401476396000},"page":"1-4","source":"Crossref","is-referenced-by-count":10,"title":["Using FPGAs to implement asynchronous pipelines"],"prefix":"10.1109","author":[{"given":"Duarte L.","family":"Oliveira","sequence":"first","affiliation":[]},{"given":"Kledermon","family":"Garcia","sequence":"additional","affiliation":[]},{"given":"Roberto","family":"d'Amore","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2002.998422"},{"year":"0","key":"22"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2005.159"},{"key":"18","first-page":"558","article-title":"Decomposition methods for library binding of speed-independent","author":"sigel","year":"1994","journal-title":"Proc Int Conf Computer-Aided Design"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2008.73"},{"key":"16","doi-asserted-by":"publisher","DOI":"10.1049\/ip-cdt:19960655"},{"journal-title":"An Architecture for High Performance Micropipeline Systems Directed to FPGAs","year":"0","author":"oliveira","key":"13"},{"key":"14","doi-asserted-by":"publisher","DOI":"10.1007\/BF01607880"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.898732"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/SOCDC.2008.4815633"},{"journal-title":"Principles of Digital Design","year":"1997","author":"gajski","key":"21"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2004.1347969"},{"journal-title":"Synthesis of Self-Timed VLSI Circuits from Graph-Theory Specifications","year":"1987","author":"chu","key":"20"},{"key":"2","doi-asserted-by":"publisher","DOI":"10.1109\/TIE.2007.898279"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1109\/5.573739"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.902206"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/92.502196"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/63526.63532"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4757-3385-3"},{"journal-title":"Asynchronous Circuit Design","year":"2004","author":"myers","key":"4"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2007.902206"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/4.720411"}],"event":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems (LASCAS)","start":{"date-parts":[[2014,2,25]]},"location":"Santiago, Chile","end":{"date-parts":[[2014,2,28]]}},"container-title":["2014 IEEE 5th Latin American Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6815880\/6820243\/06820272.pdf?arnumber=6820272","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T18:53:52Z","timestamp":1490295232000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6820272\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/lascas.2014.6820272","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}