{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,8]],"date-time":"2024-09-08T02:23:09Z","timestamp":1725762189878},"reference-count":19,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2014,2]]},"DOI":"10.1109\/lascas.2014.6820310","type":"proceedings-article","created":{"date-parts":[[2014,5,30]],"date-time":"2014-05-30T18:59:56Z","timestamp":1401476396000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["Comparing high-performance cells in CMOS bulk and FinFET technologies"],"prefix":"10.1109","author":[{"given":"Cristina","family":"Meinhardt","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ricardo","family":"Reis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"19","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537930"},{"key":"17","doi-asserted-by":"publisher","DOI":"10.5120\/5812-8104"},{"key":"18","doi-asserted-by":"publisher","DOI":"10.1145\/2228360.2228414"},{"key":"15","doi-asserted-by":"publisher","DOI":"10.1109\/5.915374"},{"key":"16","first-page":"207","article-title":"FinFETs for nanoscale CMOS digital integrated circuits","author":"king","year":"2005","journal-title":"Proc Int Conf Computer-Aided Design"},{"key":"13","doi-asserted-by":"publisher","DOI":"10.1109\/LASCAS.2013.6519063"},{"year":"0","key":"14"},{"key":"11","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"12","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2003.1240929"},{"key":"3","doi-asserted-by":"publisher","DOI":"10.1109\/FPT.2002.1188690"},{"key":"2","article-title":"Layout printability verification and physical design regularity: Roadmap enablers for the next decade","author":"capodieci","year":"2006","journal-title":"Proc EDPS"},{"key":"1","doi-asserted-by":"publisher","DOI":"10.1561\/1000000015"},{"key":"10","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS.2007.4511234"},{"key":"7","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2013.6523642"},{"key":"6","doi-asserted-by":"publisher","DOI":"10.1145\/981066.981087"},{"key":"5","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2214491"},{"key":"4","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.50"},{"key":"9","doi-asserted-by":"publisher","DOI":"10.1145\/2024724.2024743"},{"key":"8","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2011.5722217"}],"event":{"name":"2014 IEEE 5th Latin American Symposium on Circuits and Systems (LASCAS)","start":{"date-parts":[[2014,2,25]]},"location":"Santiago, Chile","end":{"date-parts":[[2014,2,28]]}},"container-title":["2014 IEEE 5th Latin American Symposium on Circuits and Systems"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/6815880\/6820243\/06820310.pdf?arnumber=6820310","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,23]],"date-time":"2017-03-23T19:01:54Z","timestamp":1490295714000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6820310\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2014,2]]},"references-count":19,"URL":"https:\/\/doi.org\/10.1109\/lascas.2014.6820310","relation":{},"subject":[],"published":{"date-parts":[[2014,2]]}}}