{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,28]],"date-time":"2025-10-28T10:44:55Z","timestamp":1761648295781,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/lascas.2015.7250433","type":"proceedings-article","created":{"date-parts":[[2015,9,11]],"date-time":"2015-09-11T00:33:59Z","timestamp":1441931639000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["A study on buffer distribution for RRAM-based FPGA routing structures"],"prefix":"10.1109","author":[{"given":"Somayyeh Rahimian","family":"Omam","sequence":"first","affiliation":[]},{"given":"Xifan","family":"Tang","sequence":"additional","affiliation":[]},{"given":"Pierre-Emmanuel","family":"Gaillardon","sequence":"additional","affiliation":[]},{"given":"Giovanni","family":"De Micheli","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","first-page":"878","article-title":"A High-Speed 7.2-ns Read-Write Random Access 4-Mb Embedded Resistive RAM (ReRAM) Macro Using Process-Variation-Tolerant Current-Mode Read Schemes","volume":"48","author":"meng-fan","year":"2013","journal-title":"IEEE JSSCC"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/ISSCC.2014.6757460"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1063\/1.1697872"},{"doi-asserted-by":"publisher","key":"ref13","DOI":"10.1109\/TED.2013.2287755"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/NANOARCH.2011.5941485"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1145\/2145694.2145708"},{"year":"1991","author":"yang","article-title":"Logic Synthesis and Optimization Benchmarks User Guide Version 3.0, MCNC","key":"ref16"},{"year":"0","journal-title":"ABC A System for Sequential Synthesis and Verification","key":"ref17"},{"key":"ref4","article-title":"Nonvolatile 3D-FPGA with monolithically stacked RRAM-based configuration memory","author":"young","year":"2012","journal-title":"ISSCC Tech Dig"},{"key":"ref3","article-title":"rFGA: CMOS-nano hybrid FPGA using RRAM components","author":"liu","year":"2008","journal-title":"NANOARCH Tech Dig"},{"doi-asserted-by":"publisher","key":"ref6","DOI":"10.1109\/VLSI-SoC.2012.6379012"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/ICECS.2010.5724454"},{"doi-asserted-by":"publisher","key":"ref8","DOI":"10.1109\/TVLSI.2013.2259512"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/TNANO.2012.2226747"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1007\/978-1-4615-5145-4"},{"key":"ref1","first-page":"1481","article-title":"A Low-Power Field-Programmable Gate Array Routing Fabric","volume":"17","author":"lin","year":"2009","journal-title":"IEEE TVLSI"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/ISSCC.2011.5746281"}],"event":{"name":"2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS 2015)","start":{"date-parts":[[2015,2,24]]},"location":"Montevideo, Uruguay","end":{"date-parts":[[2015,2,27]]}},"container-title":["2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7235122\/7250401\/07250433.pdf?arnumber=7250433","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T21:51:32Z","timestamp":1490392292000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7250433\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/lascas.2015.7250433","relation":{},"subject":[],"published":{"date-parts":[[2015,2]]}}}