{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:58:53Z","timestamp":1729663133087,"version":"3.28.0"},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,2]]},"DOI":"10.1109\/lascas.2015.7250454","type":"proceedings-article","created":{"date-parts":[[2015,9,11]],"date-time":"2015-09-11T04:33:59Z","timestamp":1441946039000},"page":"1-4","source":"Crossref","is-referenced-by-count":2,"title":["Overhead for independent net approach for Global Routing"],"prefix":"10.1109","author":[{"given":"Diego","family":"Tumelero","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Guilherme","family":"Bontorin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Ricardo","family":"Reis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/1837274.1837323"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2013.6657028"},{"key":"ref12","doi-asserted-by":"crossref","first-page":"709","DOI":"10.1109\/TCAD.2012.2235124","article-title":"NCTU-GR 2.0: Multithreaded Collision-Aware Global Routing With Bounded-Length Maze Routing","volume":"32","author":"liu","year":"2013","journal-title":"IEEE Trans Comput Des Integr Circuits Syst"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2013.70"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2014.6742945"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2205717"},{"journal-title":"Novos algoritmos para roteamento de circuitos VLSI","year":"2001","author":"johann","key":"ref16"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757353"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/1353629.1353663"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ASIC.1993.410811"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.2011.6105345"},{"journal-title":"Roteamento Global de Circuitos VLSI","year":"2012","author":"reimann","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1353629.1353662"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1231996.1232029"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.1985.1270096"},{"journal-title":"Highly Parallel Computing","year":"1989","author":"almasi","key":"ref9"}],"event":{"name":"2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS 2015)","start":{"date-parts":[[2015,2,24]]},"location":"Montevideo, Uruguay","end":{"date-parts":[[2015,2,27]]}},"container-title":["2015 IEEE 6th Latin American Symposium on Circuits & Systems (LASCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7235122\/7250401\/07250454.pdf?arnumber=7250454","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T19:17:54Z","timestamp":1498245474000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7250454\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,2]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/lascas.2015.7250454","relation":{},"subject":[],"published":{"date-parts":[[2015,2]]}}}