{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,9,22]],"date-time":"2026-09-22T08:46:13Z","timestamp":1790066773389,"version":"4.0.1"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,2]]},"DOI":"10.1109\/lascas.2016.7451035","type":"proceedings-article","created":{"date-parts":[[2016,4,14]],"date-time":"2016-04-14T16:19:48Z","timestamp":1460650788000},"page":"163-166","source":"Crossref","is-referenced-by-count":5,"title":["Reducing the number of transistors with gate clustering"],"prefix":"10.1109","author":[{"given":"Calebe","family":"Conceicao","sequence":"first","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Gracieli","family":"Posser","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]},{"given":"Ricardo","family":"Reis","sequence":"additional","affiliation":[],"role":[{"vocabulary":"crossref","role":"author"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1988.122551"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-35311-1_25"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/NANO.2011.6144656"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ISVLSI.2014.79"},{"key":"ref11","article-title":"Sis: A system for sequential circuit synthesis","author":"sentovich","year":"1992"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/SBCCI.1999.803115"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2011.5938108"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/1973009.1973040"},{"key":"ref2","author":"lavagno","year":"2006","journal-title":"EDA for IC Implementation Circuit Design and Process Technology"},{"key":"ref9","author":"rabaey","year":"2002","journal-title":"Digital Integrated Circuits"},{"key":"ref1","author":"micheli","year":"1994","journal-title":"Synthesis and Optimization of Digital Circuits"}],"event":{"name":"2016 IEEE 7th Latin American Symposium on Circuits & Systems (LASCAS)","location":"Florianopolis, Brazil","start":{"date-parts":[[2016,2,28]]},"end":{"date-parts":[[2016,3,2]]}},"container-title":["2016 IEEE 7th Latin American Symposium on Circuits &amp; Systems (LASCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7447194\/7450986\/7451035.pdf?arnumber=7451035","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,29]],"date-time":"2016-09-29T20:17:57Z","timestamp":1475180277000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7451035\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,2]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/lascas.2016.7451035","relation":{},"subject":[],"published":{"date-parts":[[2016,2]]}}}