{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,30]],"date-time":"2025-10-30T22:38:22Z","timestamp":1761863902809,"version":"3.28.0"},"reference-count":10,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,2]]},"DOI":"10.1109\/lascas.2018.8399941","type":"proceedings-article","created":{"date-parts":[[2018,7,30]],"date-time":"2018-07-30T17:45:34Z","timestamp":1532972734000},"page":"1-5","source":"Crossref","is-referenced-by-count":6,"title":["Sense amplifier offset cancellation and replica timing calibration for high-speed SRAMs"],"prefix":"10.1109","author":[{"given":"Roman","family":"Fragasse","sequence":"first","affiliation":[]},{"given":"Brian","family":"Dupaix","sequence":"additional","affiliation":[]},{"given":"Ramy","family":"Tantawy","sequence":"additional","affiliation":[]},{"given":"Todd","family":"James","sequence":"additional","affiliation":[]},{"given":"Waleed","family":"Khalil","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2008.4672108"},{"key":"ref3","first-page":"2545","volume":"46","author":"niki","year":"2011","journal-title":"A Digitized Replica Bitline Delay Technique for Random- Variation- Tolerant Timing Generation of SRAM Sense Amplifiers"},{"journal-title":"CMOS VLSI Design A Circuits and Systems Perspective","year":"2004","author":"harris","key":"ref10"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2014.2347707"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2014.6757418"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/JSSC.2012.2223036"},{"key":"ref7","doi-asserted-by":"crossref","first-page":"327","DOI":"10.1109\/ESSCIRC.1988.5468276","article-title":"Matching properties of MOS transistors","author":"pelgrom","year":"1988","journal-title":"Solid-State Circuits Conference 1988 ESSCIRC '88 Fourteenth European"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/4.75050"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1002\/9780470891179"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.705359"}],"event":{"name":"2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS)","start":{"date-parts":[[2018,2,25]]},"location":"Puerto Vallarta","end":{"date-parts":[[2018,2,28]]}},"container-title":["2018 IEEE 9th Latin American Symposium on Circuits & Systems (LASCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8392643\/8399896\/08399941.pdf?arnumber=8399941","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2020,8,23]],"date-time":"2020-08-23T22:17:48Z","timestamp":1598221068000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8399941\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,2]]},"references-count":10,"URL":"https:\/\/doi.org\/10.1109\/lascas.2018.8399941","relation":{},"subject":[],"published":{"date-parts":[[2018,2]]}}}