{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T09:31:23Z","timestamp":1730280683523,"version":"3.28.0"},"reference-count":9,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,2]]},"DOI":"10.1109\/lascas.2019.8667537","type":"proceedings-article","created":{"date-parts":[[2019,3,19]],"date-time":"2019-03-19T01:40:27Z","timestamp":1552959627000},"page":"81-84","source":"Crossref","is-referenced-by-count":2,"title":["Post-Silicon Debugging Platform with Bus Monitoring Capability to Perform Behavioral and Performance Analyses"],"prefix":"10.1109","author":[{"given":"Wilmer","family":"Ramirez","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Elkim","family":"Roa","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2010.2050501"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2011.5783747"},{"key":"ref6","first-page":"1","article-title":"IEEE Standard for Test Access Port and Boundary-Scan Architecture","year":"2013","journal-title":"IEEE Std 1149 1-2013 (Revision of IEEE Std 1149 1-2001)"},{"key":"ref5","doi-asserted-by":"crossref","first-page":"102","DOI":"10.1016\/j.micpro.2010.03.001","article-title":"Design and Implementation of Performance Analysis Unit (PAU) for AXI-based Multi-core System on a Chip (soc)","volume":"34","author":"kyung","year":"2010","journal-title":"Micro-process Microsyst"},{"journal-title":"AMBA Specification (Rev 2 0)","year":"1999","key":"ref8"},{"journal-title":"RISC-V External Debug Support 0 13","year":"2018","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ISQED.2012.6187569"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/SOCCON.2009.5398067"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"1281","DOI":"10.7873\/DATE.2015.0621","article-title":"A Breakpoint-Based Silicon Debug Technique with Cycle-Granularity for Handshake-Based SoC","author":"hsin-chen chen","year":"2015","journal-title":"Design Automation Test in Europe Conference Exhibition (DATE)"}],"event":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","start":{"date-parts":[[2019,2,24]]},"location":"Armenia, Colombia","end":{"date-parts":[[2019,2,27]]}},"container-title":["2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8666669\/8667535\/08667537.pdf?arnumber=8667537","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:13:27Z","timestamp":1657854807000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8667537\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2]]},"references-count":9,"URL":"https:\/\/doi.org\/10.1109\/lascas.2019.8667537","relation":{},"subject":[],"published":{"date-parts":[[2019,2]]}}}