{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T09:31:43Z","timestamp":1730280703306,"version":"3.28.0"},"reference-count":21,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,2,1]],"date-time":"2019-02-01T00:00:00Z","timestamp":1548979200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,2]]},"DOI":"10.1109\/lascas.2019.8667591","type":"proceedings-article","created":{"date-parts":[[2019,3,19]],"date-time":"2019-03-19T01:40:27Z","timestamp":1552959627000},"page":"225-228","source":"Crossref","is-referenced-by-count":2,"title":["A Tools Flow for Synthesis of Asynchronous Control Circuits from Extended STG Specifications"],"prefix":"10.1109","author":[{"given":"Higor A.","family":"Delsoto","sequence":"first","affiliation":[]},{"given":"Duarte L.","family":"Oliveira","sequence":"additional","affiliation":[]},{"given":"Gracieth C.","family":"Batista","sequence":"additional","affiliation":[]},{"given":"Diego A.","family":"Silva","sequence":"additional","affiliation":[]},{"given":"Leonardo","family":"Romano","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ASPDAC.2002.994891"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.1992.276300"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/ICVD.1993.669629"},{"key":"ref13","article-title":"Synthesis and Verification of Asynchronous Circuits from Graph Specifications","author":"moon","year":"1992","journal-title":"Ph D thesis"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/EDTC.1994.326848"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1016\/S0026-2714(02)00291-3"},{"key":"ref16","first-page":"1301","article-title":"XBM2PLA: A Flexible Synthesis Tool for Extended Burst Mode Machines","author":"kraus","year":"2003","journal-title":"Proc of the Design Automation and Test in Europe Conference and Exhibition"},{"key":"ref17","first-page":"300","article-title":"FPGA Implementation of Bounded Wire Delay Asynchronous Controllers from Extended Signal Transition Graph","volume":"1","author":"oliveira","year":"2009","journal-title":"XV Workshop Iberchip Buenos Aires Ediciones Cientificas Americanas"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2018.108"},{"key":"ref19","first-page":"143","article-title":"Um Fluxo de Ferramentas para S&#x00ED;ntese de Controladores ass&#x00ED;ncronos a partir de Especifica&#x00E7;&#x00F5;es XSTG","author":"delsoto","year":"2017","journal-title":"Master's thesis (in Portuguese)"},{"key":"ref4","first-page":"315","article-title":"Petrify: a tool for manipulating concurrent specifications and synthesis of asynchronous controllers","volume":"e80 d","author":"cortadella","year":"1997","journal-title":"IEICE Trans on Information and Systems"},{"journal-title":"Asynchronous Circuit Design","year":"2004","author":"myers","key":"ref3"},{"key":"ref6","doi-asserted-by":"crossref","first-page":"101","DOI":"10.1109\/43.743711","article-title":"Automatic Synthesis of Extended Burst-Mode Circuits: Part I (Specification and Hazard-.Free Implementation), Part II (Automatic Synthesis)","volume":"18","author":"yun","year":"1999","journal-title":"IEEE Trans on CAD of integrated circuit and systems"},{"key":"ref5","first-page":"333","article-title":"WORKCRAFT &#x2013; A Framework for Interpreter Graph Models","author":"poliakov","year":"2009","journal-title":"30th Int Conf PETRI NETS Springer-Verlag"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/2660540.2661007"},{"key":"ref7","article-title":"Automatic Synthesis of Burst-Mode Asynchronous Controllers","author":"nowick","year":"1993","journal-title":"PhD thesis"},{"key":"ref2","article-title":"Synthesis of Self-Timed VLSI Circuits from Graph-Theoric Specifications","author":"t \u2013a","year":"1987","journal-title":"PhD thesis"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ICSAMOS.2006.300825"},{"key":"ref9","article-title":"Sequential Optimization of Asynchronous and Synchronous Finite-State Machine","author":"fuhrer","year":"1999","journal-title":"Ph D thesis"},{"journal-title":"Technical Report","article-title":"I2C-bus Compatible ICs","year":"0","key":"ref20"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2002.804103"}],"event":{"name":"2019 IEEE 10th Latin American Symposium on Circuits & Systems (LASCAS)","start":{"date-parts":[[2019,2,24]]},"location":"Armenia, Colombia","end":{"date-parts":[[2019,2,27]]}},"container-title":["2019 IEEE 10th Latin American Symposium on Circuits &amp; Systems (LASCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8666669\/8667535\/08667591.pdf?arnumber=8667591","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,15]],"date-time":"2022-07-15T03:14:07Z","timestamp":1657854847000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8667591\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,2]]},"references-count":21,"URL":"https:\/\/doi.org\/10.1109\/lascas.2019.8667591","relation":{},"subject":[],"published":{"date-parts":[[2019,2]]}}}