{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,4]],"date-time":"2025-12-04T10:01:48Z","timestamp":1764842508984,"version":"3.37.3"},"reference-count":13,"publisher":"IEEE","license":[{"start":{"date-parts":[[2021,2,21]],"date-time":"2021-02-21T00:00:00Z","timestamp":1613865600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2021,2,21]],"date-time":"2021-02-21T00:00:00Z","timestamp":1613865600000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001659","name":"Deutsche Forschungsgemeinschaft (DFG)","doi-asserted-by":"publisher","award":["FE 412\/8-1,RE 4182\/2-1"],"award-info":[{"award-number":["FE 412\/8-1,RE 4182\/2-1"]}],"id":[{"id":"10.13039\/501100001659","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2021,2,21]]},"DOI":"10.1109\/lascas51355.2021.9459159","type":"proceedings-article","created":{"date-parts":[[2021,6,28]],"date-time":"2021-06-28T22:30:32Z","timestamp":1624919432000},"page":"1-4","source":"Crossref","is-referenced-by-count":6,"title":["Simulating large neural networks embedding MLC RRAM as weight storage considering device variations"],"prefix":"10.1109","author":[{"given":"Markus","family":"Fritscher","sequence":"first","affiliation":[{"name":"Chair for Computer Architecture, Friedrich-Alexander-Universit&#x00E4;t,Erlangen,N&#x00FC;rnberg"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Johannes","family":"Kn\u00f6dtel","sequence":"additional","affiliation":[{"name":"Chair for Computer Architecture, Friedrich-Alexander-Universit&#x00E4;t,Erlangen,N&#x00FC;rnberg"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Daniel","family":"Reiser","sequence":"additional","affiliation":[{"name":"Chair for Computer Architecture, Friedrich-Alexander-Universit&#x00E4;t,Erlangen,N&#x00FC;rnberg"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Maen","family":"Mallah","sequence":"additional","affiliation":[{"name":"Fraunhofer IIS,Erlangen"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Stefan","family":"Pechmann","sequence":"additional","affiliation":[{"name":"Chair of Communications Electronics, Universit&#x00E4;t Bayreuth"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Dietmar","family":"Fey","sequence":"additional","affiliation":[{"name":"Chair for Computer Architecture, Friedrich-Alexander-Universit&#x00E4;t,Erlangen,N&#x00FC;rnberg"}],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Marc","family":"Reichenbach","sequence":"additional","affiliation":[{"name":"Chair for Computer Architecture, Friedrich-Alexander-Universit&#x00E4;t,Erlangen,N&#x00FC;rnberg"}],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1038\/s41598-017-17785-1"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/AICAS.2019.8771544"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2016.7527252"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICECS46596.2019.8964856"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IranianCEE.2012.6292348"},{"key":"ref6","article-title":"RAPIDNN: In-Memory Deep Neural Network Acceleration Framework","volume":"abs\/1806.05794","author":"Imani","year":"2018","journal-title":"CoRR"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2017.2729466"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/3240765.3240800"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/iscas45731.2020.9180810"},{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2019.2922838"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2020.3004666"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MOCAST49295.2020.9200241"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2015.2442412"}],"event":{"name":"2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS)","start":{"date-parts":[[2021,2,21]]},"location":"Arequipa, Peru","end":{"date-parts":[[2021,2,24]]}},"container-title":["2021 IEEE 12th Latin America Symposium on Circuits and System (LASCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/9458948\/9459110\/09459159.pdf?arnumber=9459159","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2024,8,31]],"date-time":"2024-08-31T05:22:18Z","timestamp":1725081738000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9459159\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2021,2,21]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/lascas51355.2021.9459159","relation":{},"subject":[],"published":{"date-parts":[[2021,2,21]]}}}