{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T09:37:24Z","timestamp":1775036244185,"version":"3.50.1"},"reference-count":15,"publisher":"IEEE","license":[{"start":{"date-parts":[[2026,2,24]],"date-time":"2026-02-24T00:00:00Z","timestamp":1771891200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2026,2,24]],"date-time":"2026-02-24T00:00:00Z","timestamp":1771891200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2026,2,24]]},"DOI":"10.1109\/lascas67804.2026.11457146","type":"proceedings-article","created":{"date-parts":[[2026,3,31]],"date-time":"2026-03-31T19:50:57Z","timestamp":1774986657000},"page":"1-5","source":"Crossref","is-referenced-by-count":0,"title":["Strategies for Scaling Up RL-Based Multiplier Architectures to Higher Bit-Widths"],"prefix":"10.1109","author":[{"given":"Ronny Alberto Rueda","family":"M\u00e9ndez","sequence":"first","affiliation":[{"name":"Universidad Nacional de Colombia,Department of Electrical and Electronic Engineering,Bogotá,Colombia"}]},{"given":"Juan Sebasti\u00e1n Caviedes","family":"Bernal","sequence":"additional","affiliation":[{"name":"Universidad Nacional de Colombia,Department of Electrical and Electronic Engineering,Bogotá,Colombia"}]},{"given":"Johan Sebasti\u00e1n Eslava","family":"Garz\u00f3n","sequence":"additional","affiliation":[{"name":"Universidad Nacional de Colombia,Department of Electrical and Electronic Engineering,Bogotá,Colombia"}]}],"member":"263","reference":[{"key":"ref1","volume-title":"Computer Arithmetic: Algorithms and Hardware Designs","author":"Parhami","year":"2010"},{"key":"ref2","volume-title":"Approximate computing techniques: from component-to application-level, eng.","year":"2022"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/tnn.1998.712192"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.13140\/RG.2.2.18893.74727"},{"key":"ref5","article-title":"Learning algorithmic reasoning with neural execution of programs","volume-title":"International Conference on Learning Representations (ICLR)","author":"Kaiser","year":"2020"},{"key":"ref6","author":"Zaremba","year":"2016","journal-title":"Reinforcement learning neural turing machines"},{"key":"ref7","article-title":"Gymnasium documentation","volume-title":"Ultimo acceso: 27 de junio de 2025","author":"Foundation","year":"2025"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/mspct.2009.5164200"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1587\/elex.12.20150450"},{"key":"ref10","volume-title":"aditya1746, Gaussian-Filter-Verilog-Implementation-, GitHub repository, \u00daltimo commit 2024, usado para implementar un filtro Gaussiano en Verilog para procesamiento de im\u00e1genes (grayscale y color)","year":"2024"},{"key":"ref11","article-title":"Pygame Community, Pygame news","volume-title":"Ultimo acceso: 27 de junio de 2025","year":"2025"},{"key":"ref12","article-title":"Icarus verilog: An open source verilog compiler and simulator","volume-title":"Repositorio GitHub. \u00daltimo acceso: 27 de junio de 2025","author":"Williams","year":"2025"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/iscmi67495.2025.11358612"},{"key":"ref14","volume-title":"OpenLANE: The Open-Source Digital ASIC Implementation Flow","author":"Ghazy"},{"key":"ref15","article-title":"Google, and Efabless, Sky130 pdk documentation and open-source flow","volume-title":"Repositorio y gu\u00edas del PDK open-source; incluye flujo OpenLANE desarrollado por Efabless. \u00daltimo acceso: 27 de junio de 2025","author":"Foundry","year":"2025"}],"event":{"name":"2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)","location":"Arequipa, Peru","start":{"date-parts":[[2026,2,24]]},"end":{"date-parts":[[2026,2,27]]}},"container-title":["2026 IEEE 17th Latin America Symposium on Circuits and System (LASCAS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx8\/11457069\/11457071\/11457146.pdf?arnumber=11457146","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2026,4,1]],"date-time":"2026-04-01T06:54:20Z","timestamp":1775026460000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/11457146\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2026,2,24]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/lascas67804.2026.11457146","relation":{},"subject":[],"published":{"date-parts":[[2026,2,24]]}}}