{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T05:41:32Z","timestamp":1729662092092,"version":"3.28.0"},"reference-count":27,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2011,3]]},"DOI":"10.1109\/latw.2011.5985901","type":"proceedings-article","created":{"date-parts":[[2011,8,16]],"date-time":"2011-08-16T15:29:25Z","timestamp":1313508565000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Reliability enhancement via Sleep Transistors"],"prefix":"10.1109","author":[{"given":"Frank Sill","family":"Torres","sequence":"first","affiliation":[]},{"given":"Claas","family":"Cornelius","sequence":"additional","affiliation":[]},{"given":"Dirk","family":"Timmermann","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"year":"2002","key":"ref10","article-title":"Failure Mechanisms and Models for Semiconductor Devices"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1147\/rd.462.0265"},{"key":"ref12","article-title":"Method of determining reliability screens for time dependent reliability breakdown","author":"crook","year":"1979","journal-title":"IRPS"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1016\/S0038-1101(02)00151-X"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2009.2015160"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1049\/el.2010.1971"},{"key":"ref16","doi-asserted-by":"crossref","first-page":"90","DOI":"10.1109\/LPE.2000.155259","article-title":"gated-v\/sub dd\/: a circuit technique to reduce leakage in deep-submicron cache memories","author":"powell","year":"2000","journal-title":"ISLPED 00 the 2000 International Symposium on Low Power Electronics and Design (Cat No 00TH8514) LPE-00"},{"key":"ref17","article-title":"Sleep transistor sizing using timing criticality and temporal currents","author":"ramalingam","year":"0","journal-title":"Proc ASP-DAC"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1145\/1146909.1146943"},{"year":"2004","key":"ref19","article-title":"Designing for power - intel leadership in power efficient silicon and system design"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/MC.2005.70"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2003.1250804"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2006.12"},{"key":"ref6","article-title":"Adaptive body bias for reducing impacts of die-to-die and within-die parameter variations on microprocessor frequency and leakage","volume":"37","author":"tschanz","year":"2002","journal-title":"Journal of Solid-State Circuits (JSSC)"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/383082.383133"},{"key":"ref8","article-title":"RAMP: A Model for Reliability Aware Microprocessor Design","author":"srinivasan","year":"2003","journal-title":"IBM Research Report RC23048"},{"article-title":"Fault-tolerant systems","year":"2007","author":"koren","key":"ref7"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2006.15"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/T-ED.1969.16754"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2004.1311888"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1404371.1404407"},{"key":"ref22","first-page":"1047","article-title":"Modeling and minimization of PMOS NBTI effect for robust nanometer design","author":"vattikonda","year":"0","journal-title":"Proceedings of the 43rd Annual Design Automation Conference (DAC'06)"},{"key":"ref21","doi-asserted-by":"publisher","DOI":"10.1023\/A:1024683708105"},{"key":"ref24","first-page":"58","article-title":"Circuit realiability simulation based on Verilog-A","author":"kole","year":"0","journal-title":"Proc BMAS'07"},{"key":"ref23","first-page":"731","article-title":"An overview of non-volatile memory technology and the implication for tools and architectures","author":"li","year":"0","journal-title":"2009 Design, Automation & Test in Europe Conference & Exhibition"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1109\/TED.2006.884077"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/54.785838"}],"event":{"name":"2011 12th Latin American Test Workshop - LATW","start":{"date-parts":[[2011,3,27]]},"location":"Beach of Porto de Galinhas, Brazil","end":{"date-parts":[[2011,3,30]]}},"container-title":["2011 12th Latin American Test Workshop (LATW)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx5\/5978853\/5985882\/05985901.pdf?arnumber=5985901","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,20]],"date-time":"2017-06-20T00:48:37Z","timestamp":1497919717000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/5985901\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2011,3]]},"references-count":27,"URL":"https:\/\/doi.org\/10.1109\/latw.2011.5985901","relation":{},"subject":[],"published":{"date-parts":[[2011,3]]}}}