{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,5]],"date-time":"2024-09-05T14:35:00Z","timestamp":1725546900491},"reference-count":13,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,3]]},"DOI":"10.1109\/latw.2015.7102411","type":"proceedings-article","created":{"date-parts":[[2015,5,8]],"date-time":"2015-05-08T15:54:45Z","timestamp":1431100485000},"page":"1-6","source":"Crossref","is-referenced-by-count":5,"title":["Virtual reconfigurable scan-chains on FPGAs for optimized board test"],"prefix":"10.1109","author":[{"given":"Igor","family":"Aleksejev","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Sergei","family":"Devadze","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Artur","family":"Jutman","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Konstantin","family":"Shibin","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"ASSET InterTech","article-title":"How to test high-speed memory with non-intrusive embedded instruments","year":"2012","key":"ref10"},{"journal-title":"Spansion Inc S29AL008D 8MBit Flash Memory Datasheet","year":"0","key":"ref11"},{"journal-title":"Intel Inc Intel StrataFlash&#x00AE; Embedded Memory Datasheet","year":"0","key":"ref12"},{"journal-title":"Micron Technology M25P32 Serial Flash Memory Datasheet","year":"0","key":"ref13"},{"key":"ref4","article-title":"A novel configurable boundary-scan circuit design of SRAM-based FPGA","author":"guo","year":"2011","journal-title":"Proceedings of CSAE"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.1991.519698"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401571"},{"key":"ref5","article-title":"A novel structure of dynamic configurable scan chain bypassing unconcerned segments on the fly","author":"wang","year":"2013","journal-title":"Proc of ASICON"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2012.6261241"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2005.1584043"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/ICCAD.1993.580166"},{"year":"0","key":"ref1"},{"journal-title":"Intellitech Corp","article-title":"Infrastructure IP for Programming and Test of in-system Memory Devices","year":"2003","key":"ref9"}],"event":{"name":"2015 16th Latin-American Test Symposium (LATS)","start":{"date-parts":[[2015,3,25]]},"location":"Puerto Vallarta, Mexico","end":{"date-parts":[[2015,3,27]]}},"container-title":["2015 16th Latin-American Test Symposium (LATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7101754\/7102396\/07102411.pdf?arnumber=7102411","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T18:14:28Z","timestamp":1490379268000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7102411\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3]]},"references-count":13,"URL":"https:\/\/doi.org\/10.1109\/latw.2015.7102411","relation":{},"subject":[],"published":{"date-parts":[[2015,3]]}}}