{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,3,31]],"date-time":"2025-03-31T21:44:48Z","timestamp":1743457488964},"reference-count":22,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,3]]},"DOI":"10.1109\/latw.2015.7102510","type":"proceedings-article","created":{"date-parts":[[2015,5,8]],"date-time":"2015-05-08T11:54:45Z","timestamp":1431086085000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["Test compression for circuits with multiple scan chains"],"prefix":"10.1109","author":[{"given":"Ondrej","family":"Novak","sequence":"first","affiliation":[]},{"given":"Jiri","family":"Jen\u00edcek","sequence":"additional","affiliation":[]},{"given":"Martin","family":"Rozkovec","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"doi-asserted-by":"publisher","key":"ref10","DOI":"10.1109\/TCAD.2006.882509"},{"doi-asserted-by":"publisher","key":"ref11","DOI":"10.1109\/TVLSI.2010.2079961"},{"doi-asserted-by":"publisher","key":"ref12","DOI":"10.1109\/ATS.2001.990304"},{"key":"ref13","first-page":"188","article-title":"Test-Architecture Optimization and Test Scheduling for SOCs with Core-Level Expansion of Compressed Test Patterns","author":"larsson","year":"0","journal-title":"Design Automation and Test in Europe 2008 DATE '08"},{"doi-asserted-by":"publisher","key":"ref14","DOI":"10.1109\/TEST.2009.5355555"},{"doi-asserted-by":"publisher","key":"ref15","DOI":"10.1109\/VTS.2013.6548884"},{"doi-asserted-by":"publisher","key":"ref16","DOI":"10.1109\/VTS.2002.1011104"},{"doi-asserted-by":"publisher","key":"ref17","DOI":"10.1109\/TCAD.2004.826558"},{"doi-asserted-by":"publisher","key":"ref18","DOI":"10.1109\/ISVLSI.2004.1339525"},{"doi-asserted-by":"publisher","key":"ref19","DOI":"10.1109\/DATE.2008.4484726"},{"doi-asserted-by":"publisher","key":"ref4","DOI":"10.1109\/43.875312"},{"doi-asserted-by":"publisher","key":"ref3","DOI":"10.1109\/TEST.1999.805857"},{"key":"ref6","first-page":"214","article-title":"Pseudoexhaustive Test Pattern Generation for Structured Digital Circuits","author":"golan","year":"1986","journal-title":"Proc IX International Conference on Fault Tolerant Systems and Diagnostics FTSD 9"},{"doi-asserted-by":"publisher","key":"ref5","DOI":"10.1109\/VTS.2008.42"},{"key":"ref8","first-page":"180","article-title":"Low power test data compression based on LFSR reseeding","author":"lee","year":"0","journal-title":"Computer Design VLSI in Computers and Processors 2004 ICCD 2004 Proceedings IEEE International Conference on"},{"doi-asserted-by":"publisher","key":"ref7","DOI":"10.1109\/ETS.2012.6233003"},{"doi-asserted-by":"publisher","key":"ref2","DOI":"10.1109\/TCAD.2011.2126574"},{"doi-asserted-by":"publisher","key":"ref1","DOI":"10.1109\/TVLSI.2006.886417"},{"doi-asserted-by":"publisher","key":"ref9","DOI":"10.1109\/TCAD.2006.882509"},{"doi-asserted-by":"publisher","key":"ref20","DOI":"10.1109\/DATE.2008.4484726"},{"doi-asserted-by":"publisher","key":"ref22","DOI":"10.1109\/TCAD.2009.2021731"},{"doi-asserted-by":"publisher","key":"ref21","DOI":"10.1109\/MDT.2006.105"}],"event":{"name":"2015 16th Latin-American Test Symposium (LATS)","start":{"date-parts":[[2015,3,25]]},"location":"Puerto Vallarta, Mexico","end":{"date-parts":[[2015,3,27]]}},"container-title":["2015 16th Latin-American Test Symposium (LATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7101754\/7102396\/07102510.pdf?arnumber=7102510","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,3,24]],"date-time":"2017-03-24T14:52:22Z","timestamp":1490367142000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7102510\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3]]},"references-count":22,"URL":"https:\/\/doi.org\/10.1109\/latw.2015.7102510","relation":{},"subject":[],"published":{"date-parts":[[2015,3]]}}}