{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,23]],"date-time":"2024-10-23T09:14:21Z","timestamp":1729674861958,"version":"3.28.0"},"reference-count":14,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2015,3]]},"DOI":"10.1109\/latw.2015.7102520","type":"proceedings-article","created":{"date-parts":[[2015,5,8]],"date-time":"2015-05-08T15:54:45Z","timestamp":1431100485000},"page":"1-6","source":"Crossref","is-referenced-by-count":1,"title":["Estimation of dynamic current waveforms using pre-characterization of standard cells"],"prefix":"10.1109","author":[{"given":"Bharath","family":"Shivashankar","sequence":"first","affiliation":[]},{"given":"Michael","family":"Skaggs","sequence":"additional","affiliation":[]},{"given":"Sushmita Kadiyala","family":"Rao","sequence":"additional","affiliation":[]},{"given":"Ryan","family":"Robucci","sequence":"additional","affiliation":[]},{"given":"Nilanjan","family":"Banerjee","sequence":"additional","affiliation":[]},{"given":"Chintan","family":"Patel","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2007.76"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2008.4484837"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2009.45"},{"key":"ref13","first-page":"597","article-title":"Fast, layout-aware validation of test-vectors for nanometer-related timing fail-ures","author":"kokrady","year":"2004","journal-title":"VLSI Design 2004 Proceedings 17th International Conference on"},{"key":"ref14","first-page":"1","article-title":"Pattern-directed circuit virtual partitioning for test power reduction","author":"xu","year":"0"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/ICCD.2000.878270"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2007.89"},{"journal-title":"CCS Timing Library Characterization Guidelines Version 3 2 Synopsys","year":"2008","key":"ref6"},{"journal-title":"Open Source ECSM Format Specification Version 2 1 Cadence","year":"2006","key":"ref5"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2012.2197427"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2010.5537092"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MDT.2010.52"},{"key":"ref1","doi-asserted-by":"crossref","first-page":"125","DOI":"10.1007\/s10836-013-5425-5","article-title":"Simulation Based Framework for Accurately Estimating Dynamic Pow-er-Supply Noise and Path Delay","volume":"30","author":"rao","year":"2014","journal-title":"Journal of Electronic Testing"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2013.6562657"}],"event":{"name":"2015 16th Latin-American Test Symposium (LATS)","start":{"date-parts":[[2015,3,25]]},"location":"Puerto Vallarta, Mexico","end":{"date-parts":[[2015,3,27]]}},"container-title":["2015 16th Latin-American Test Symposium (LATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7101754\/7102396\/07102520.pdf?arnumber=7102520","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,6,23]],"date-time":"2017-06-23T11:12:54Z","timestamp":1498216374000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7102520\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,3]]},"references-count":14,"URL":"https:\/\/doi.org\/10.1109\/latw.2015.7102520","relation":{},"subject":[],"published":{"date-parts":[[2015,3]]}}}