{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,22]],"date-time":"2024-10-22T15:15:55Z","timestamp":1729610155001,"version":"3.28.0"},"reference-count":17,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2016,4]]},"DOI":"10.1109\/latw.2016.7483344","type":"proceedings-article","created":{"date-parts":[[2016,6,23]],"date-time":"2016-06-23T12:48:27Z","timestamp":1466686107000},"page":"81-86","source":"Crossref","is-referenced-by-count":0,"title":["A methodology for NBTI circuit reliability at reduced power consumption using dual supply voltage"],"prefix":"10.1109","author":[{"given":"Freddy","family":"Forero","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Andres","family":"Gomez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Victor","family":"Champac","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1007\/978-0-387-68953-1_8"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1016\/j.microrel.2006.10.012"},{"key":"ref12","article-title":"Temperature Impact on NBTI Modeling in the Framework of Technology Scaling","volume":"24","author":"khan","year":"2010","journal-title":"2nd HiPEAC Workshop on Design for Reliability"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1524\/itit.2010.0589"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1007\/978-3-540-30205-6_44"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ISCAS.2007.378489"},{"journal-title":"Freescale Semiconductor Inc","article-title":"Thermal Analysis of Semiconductor Systems","year":"0","key":"ref16"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/DATE.2007.364517"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/IOLTS.2011.5993802"},{"key":"ref3","first-page":"216","article-title":"Efficient Transistor-Level Sizing Technique under Temporal Performance Degradation due to NBTI","author":"kang","year":"2007","journal-title":"Computer Design 2006 ICCD 2006 International Conference on"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2015.7102405"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2014.6841926"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/TVLSI.2008.2008810"},{"key":"ref7","first-page":"1","article-title":"Temperature-aware NBTI modeling and the impact of input vector control on performance degradation","author":"yu","year":"2007","journal-title":"Design Automation & Test in Europe Conference & Exhibition 2007"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2015.7102496"},{"key":"ref1","article-title":"CMOS scaling impacts on Reliability, What do we understand?","author":"khan","year":"2008","journal-title":"Proc 19th Annual Workshop on circuits systems and signal processing ProRisc 2008"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/ISSCC.2003.1234226"}],"event":{"name":"2016 17th Latin-American Test Symposium (LATS)","start":{"date-parts":[[2016,4,6]]},"location":"Foz do Iguacu, Brazil","end":{"date-parts":[[2016,4,8]]}},"container-title":["2016 17th Latin-American Test Symposium (LATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7477975\/7483323\/07483344.pdf?arnumber=7483344","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2016,9,29]],"date-time":"2016-09-29T11:02:47Z","timestamp":1475146967000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7483344\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2016,4]]},"references-count":17,"URL":"https:\/\/doi.org\/10.1109\/latw.2016.7483344","relation":{},"subject":[],"published":{"date-parts":[[2016,4]]}}}