{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,10,25]],"date-time":"2025-10-25T12:23:26Z","timestamp":1761395006144},"reference-count":15,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.1109\/latw.2017.7906755","type":"proceedings-article","created":{"date-parts":[[2017,4,24]],"date-time":"2017-04-24T21:12:09Z","timestamp":1493068329000},"page":"1-6","source":"Crossref","is-referenced-by-count":11,"title":["Analysis of short defects in FinFET based logic cells"],"prefix":"10.1109","author":[{"given":"Freddy","family":"Forero","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Jean-Marc","family":"Galliere","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Michell","family":"Renovell","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Victor","family":"Champac","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/EWDTS.2014.7027088"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2012.6241865"},{"key":"ref12","first-page":"1","article-title":"Elimination of tungsten-voids in middle-of-line contacts for advanced planar cmos and finfet technology","author":"peng","year":"0","journal-title":"2016 China Semiconductor Technology International Conference (CSTIC)"},{"key":"ref13","first-page":"3.7.1","article-title":"A 14nm logic technology featuring 2nd-generation finfet, air-gapped interconnects, self-aligned double patterning and a 0.0588 µm2 sram cell size","author":"natarajan","year":"0","journal-title":"2014 IEEE International Electron Devices Meeting"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/IRPS.2013.6531970"},{"year":"0","key":"ref15"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TNANO.2011.2169807"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/NANOARCH.2010.5510927"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2015.38"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2012.6401565"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/EWDTS.2015.7493149"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/LATW.2016.7483352"},{"key":"ref2","article-title":"New approaches to improving quality and accelerating yield ramp for finfet technology","author":"sawicki","year":"2013","journal-title":"Semicon West"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2007.4419001"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/VTS.2014.6818747"}],"event":{"name":"2017 18th IEEE Latin American Test Symposium (LATS)","start":{"date-parts":[[2017,3,13]]},"location":"Bogota, Colombia","end":{"date-parts":[[2017,3,15]]}},"container-title":["2017 18th IEEE Latin American Test Symposium (LATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7899159\/7906734\/07906755.pdf?arnumber=7906755","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,12,13]],"date-time":"2017-12-13T20:13:06Z","timestamp":1513195986000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7906755\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":15,"URL":"https:\/\/doi.org\/10.1109\/latw.2017.7906755","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}