{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,4]],"date-time":"2024-09-04T00:10:42Z","timestamp":1725408642837},"reference-count":16,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2017,3]]},"DOI":"10.1109\/latw.2017.7906759","type":"proceedings-article","created":{"date-parts":[[2017,4,24]],"date-time":"2017-04-24T21:12:09Z","timestamp":1493068329000},"page":"1-6","source":"Crossref","is-referenced-by-count":2,"title":["On the detection of board delay faults through the execution of functional programs"],"prefix":"10.1109","author":[{"given":"G.","family":"An","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"R.","family":"Cantoro","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"E.","family":"Sanchez","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"M. Sonza","family":"Reorda","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","article-title":"Memory testing with a RISC microcontroller","author":"van","year":"2010","journal-title":"Proc of Design Automation and Test in Europe Dresden"},{"journal-title":"Testing Semiconductor Memories Theory and Practice","year":"1991","author":"van de goor","key":"ref11"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2481859"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2015.2432142"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2006.297632"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/ATS.2014.62"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2002.1041863"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2015.2498546"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/TNS.2015.2484842"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1023\/A:1008305507376"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/DFTVS.2001.966775"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ETS.2016.7519295"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/DSD.2011.76"},{"journal-title":"Introduction to the WISHBONE Bus Interface","year":"0","key":"ref2"},{"journal-title":"OpenRISC 1200 IP Core Specification","year":"0","key":"ref1"},{"key":"ref9","article-title":"Functional Test Coverage Assessment Project","author":"taylor","year":"2009","journal-title":"IEEE 8th International Board Test Workshop (BTW&#x2019;2009)"}],"event":{"name":"2017 18th IEEE Latin American Test Symposium (LATS)","start":{"date-parts":[[2017,3,13]]},"location":"Bogota, Colombia","end":{"date-parts":[[2017,3,15]]}},"container-title":["2017 18th IEEE Latin American Test Symposium (LATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/7899159\/7906734\/07906759.pdf?arnumber=7906759","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2017,5,15]],"date-time":"2017-05-15T20:12:35Z","timestamp":1494879155000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7906759\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,3]]},"references-count":16,"URL":"https:\/\/doi.org\/10.1109\/latw.2017.7906759","relation":{},"subject":[],"published":{"date-parts":[[2017,3]]}}}