{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,10,30]],"date-time":"2024-10-30T09:32:10Z","timestamp":1730280730048,"version":"3.28.0"},"reference-count":20,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/latw.2018.8347238","type":"proceedings-article","created":{"date-parts":[[2018,4,26]],"date-time":"2018-04-26T18:51:33Z","timestamp":1524768693000},"page":"1-6","source":"Crossref","is-referenced-by-count":5,"title":["Direct optimization of a PCI express link equalization in industrial post-silicon validation"],"prefix":"10.1109","author":[{"given":"Francisco E.","family":"Rangel-Patino","sequence":"first","affiliation":[]},{"given":"Jose E.","family":"Rayas-Sanchez","sequence":"additional","affiliation":[]},{"given":"Edgar A.","family":"Vega-Ochoa","sequence":"additional","affiliation":[]},{"given":"Nagib","family":"Hakim","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"journal-title":"FPGAs at 40 nm and > 10 Gbps Jitter- Signal integrity- Power- and Process-Optimized Transceivers","article-title":"ALTERA","year":"2013","key":"ref10"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/ICCDCS.2017.7959697"},{"journal-title":"High Speed Serdes Devices and Applications","year":"2008","author":"stauffer","key":"ref12"},{"key":"ref13","article-title":"PCI Express 3.0 Equalization: The Mystery Unsolved","author":"fruit","year":"0","journal-title":"[Online] White Paper Logic Fruit Technologies"},{"journal-title":"Designing to the new PCI Express 3 0 equalization requirements","article-title":"PCI SIG Org","year":"2012","key":"ref14"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VLSID.2006.159"},{"key":"ref16","first-page":"212","article-title":"A holistic formulation for system margining and jitter tolerance optimization in industrial post-silicon validation","volume":"8","author":"rangel-pati\u00f1o","year":"2017","journal-title":"IEEE Transactions on Emerging Topics in Computing"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/321062.321069"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1137\/S1052623496303470"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/TMTT.2017.2701368"},{"key":"ref4","article-title":"PCI express 4.0 electrical previews","author":"gonzales","year":"2015","journal-title":"PCI Developers' Conference"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1364\/OFC.2017.W4I.3"},{"key":"ref6","article-title":"Serial data equalization","author":"casper","year":"2007","journal-title":"12th Conference and Technology Exhibition DesignCon 2007"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/ICCE.2015.7066414"},{"journal-title":"Jitter Noise and Signal Integrity at High-Speed","year":"2007","author":"li","key":"ref8"},{"key":"ref7","article-title":"Stanford University Lecture","author":"stojanovic","year":"0","journal-title":"Modeling and Analysis of High-Speed Links"},{"journal-title":"PCI SIG Org (2017) PCI Express® Base Specification Revision 4 0 Version 1 0","year":"0","key":"ref2"},{"journal-title":"Introduction to PCI Express A Hardware and Software Developer's Guide","year":"2003","author":"wilen","key":"ref1"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/LAMC.2016.7851268"},{"journal-title":"Open-source Software for Mathematics Science and Engineering","article-title":"SciPy.org, PCI SIG Org","year":"2017","key":"ref20"}],"event":{"name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","start":{"date-parts":[[2018,3,12]]},"location":"Sao Paulo","end":{"date-parts":[[2018,3,14]]}},"container-title":["2018 IEEE 19th Latin-American Test Symposium (LATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8340944\/8347228\/08347238.pdf?arnumber=8347238","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2018,5,28]],"date-time":"2018-05-28T20:39:41Z","timestamp":1527539981000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8347238\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":20,"URL":"https:\/\/doi.org\/10.1109\/latw.2018.8347238","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}