{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,2]],"date-time":"2025-12-02T15:02:51Z","timestamp":1764687771754,"version":"3.41.0"},"reference-count":11,"publisher":"IEEE","content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2018,3]]},"DOI":"10.1109\/latw.2018.8349666","type":"proceedings-article","created":{"date-parts":[[2018,4,26]],"date-time":"2018-04-26T22:51:33Z","timestamp":1524783093000},"page":"1-6","source":"Crossref","is-referenced-by-count":13,"title":["Flexible architecture of memory BISTs"],"prefix":"10.1109","author":[{"given":"Reinaldo","family":"Silveira","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Qadeer","family":"Qureshi","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Rodrigo","family":"Zeli","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"journal-title":"ARM Limited-AMBA™3 APB Protocol ARMIHI 0024B","year":"0","key":"ref4"},{"journal-title":"IJ-TAG-Internal Joint Test Action Group IEEE Computer Society","year":"0","key":"ref3"},{"journal-title":"ARM-DDI-04381 ID062913 4 0","article-title":"ARM ARM Cortex-A15 MPCore Processor, Technical Reference Manual","year":"2013","key":"ref10"},{"key":"ref6","article-title":"Comprehensive Study on Designing Memory BIST: Algorithms, Implementations and Trade-Offs","author":"cheng","year":"2002","journal-title":"Project Report Advanced Computer Architecture Lab University of Michigan"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TCAD.2006.884415"},{"journal-title":"Freescale Semiconductor-SRS IP Interface SRS V4 0 01","year":"2007","key":"ref5"},{"journal-title":"IEEE Design & Test of Computers","article-title":"Manoj Sachdev-Open Defects in CMOS RAM Address Decoders","year":"1997","key":"ref8"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299235"},{"journal-title":"Testing Semiconductor Memories Theory and Practice","year":"1991","author":"van de goor","key":"ref2"},{"key":"ref9","doi-asserted-by":"crossref","DOI":"10.1145\/1118299.1118457","article-title":"A Memory Grouping Method for Sharing Memory BIST Logic","author":"miyazaki","year":"2006","journal-title":"Asia and South Pacific Conference on Design Automation"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.1999.766672"}],"event":{"name":"2018 IEEE 19th Latin-American Test Symposium (LATS)","start":{"date-parts":[[2018,3,12]]},"location":"Sao Paulo","end":{"date-parts":[[2018,3,14]]}},"container-title":["2018 IEEE 19th Latin-American Test Symposium (LATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8340944\/8347228\/08349666.pdf?arnumber=8349666","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2025,7,3]],"date-time":"2025-07-03T23:33:35Z","timestamp":1751585615000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8349666\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,3]]},"references-count":11,"URL":"https:\/\/doi.org\/10.1109\/latw.2018.8349666","relation":{},"subject":[],"published":{"date-parts":[[2018,3]]}}}