{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2024,9,6]],"date-time":"2024-09-06T03:43:20Z","timestamp":1725594200197},"reference-count":7,"publisher":"IEEE","license":[{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,3,1]],"date-time":"2019-03-01T00:00:00Z","timestamp":1551398400000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":[],"published-print":{"date-parts":[[2019,3]]},"DOI":"10.1109\/latw.2019.8704563","type":"proceedings-article","created":{"date-parts":[[2019,5,2]],"date-time":"2019-05-02T22:53:07Z","timestamp":1556837587000},"page":"1-4","source":"Crossref","is-referenced-by-count":0,"title":["Analog\/Mixed Signal IP DFx from a Foundry perspective"],"prefix":"10.1109","author":[{"given":"Salem","family":"Abdennadher","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Arani","family":"Sinha","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Yonghyun","family":"Kim","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TEST.2001.966682"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/CICC.2002.1012825"},{"journal-title":"Accellera Systems Initiative (Accellera) Standards","year":"2018","key":"ref6"},{"year":"0","key":"ref5"},{"journal-title":"DesignWare DDR multiPHY IP","year":"0","key":"ref7"},{"journal-title":"IP Offering Intel Website","year":"0","key":"ref2"},{"key":"ref1","article-title":"Building Winning Products with Intel&#x00AE; Advanced Technologies and Custom Foundry Platforms","author":"bohr","year":"0","journal-title":"Intel Developer Forum"}],"event":{"name":"2019 IEEE Latin American Test Symposium (LATS)","start":{"date-parts":[[2019,3,11]]},"location":"Santiago, Chile","end":{"date-parts":[[2019,3,13]]}},"container-title":["2019 IEEE Latin American Test Symposium (LATS)"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/8700506\/8704547\/08704563.pdf?arnumber=8704563","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,18]],"date-time":"2022-07-18T14:48:15Z","timestamp":1658155695000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8704563\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,3]]},"references-count":7,"URL":"https:\/\/doi.org\/10.1109\/latw.2019.8704563","relation":{},"subject":[],"published":{"date-parts":[[2019,3]]}}}