{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,27]],"date-time":"2026-02-27T15:18:04Z","timestamp":1772205484947,"version":"3.50.1"},"reference-count":16,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2015,1,1]],"date-time":"2015-01-01T00:00:00Z","timestamp":1420070400000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"DOI":"10.13039\/501100011101","name":"Intel Collaborative Research Institute for Computational Intelligence","doi-asserted-by":"crossref","id":[{"id":"10.13039\/501100011101","id-type":"DOI","asserted-by":"crossref"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2015,1,1]]},"DOI":"10.1109\/lca.2014.2319077","type":"journal-article","created":{"date-parts":[[2014,4,21]],"date-time":"2014-04-21T18:01:26Z","timestamp":1398103286000},"page":"54-57","source":"Crossref","is-referenced-by-count":5,"title":["Peripheral memory: a technique for fighting memory bandwidth bottleneck"],"prefix":"10.1109","volume":"14","author":[{"given":"Leonid","family":"Azriel","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Avi","family":"Mendelson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Uri","family":"Weiser","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","year":"0"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2007.1036"},{"key":"ref12","year":"0"},{"key":"ref13","year":"0"},{"key":"ref14","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2005.23"},{"key":"ref15","year":"0"},{"key":"ref16","year":"0"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/CLUSTR.2005.347027"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1145\/232973.232983"},{"key":"ref6","article-title":"Cache capacity and memory bandwidth scaling limits of highly threaded processors, WORKSHOP on UNIQUE CHIPS and SYSTEMS (UCAS-5)","author":"stuecheli","year":"0"},{"key":"ref5","year":"0"},{"key":"ref8","first-page":"461","article-title":"Page-flip technology for use within the Linux networking stack","volume":"2","author":"ronciak","year":"0","journal-title":"Proc Linux Symp"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/INFCOM.1999.751387"},{"key":"ref2","year":"0"},{"key":"ref1","year":"0"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1145\/290593.290602"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10208\/7128787\/06803056.pdf?arnumber=6803056","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:04:49Z","timestamp":1642003489000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/6803056\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2015,1,1]]},"references-count":16,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/lca.2014.2319077","relation":{},"ISSN":["1556-6056"],"issn-type":[{"value":"1556-6056","type":"print"}],"subject":[],"published":{"date-parts":[[2015,1,1]]}}}