{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,3,24]],"date-time":"2026-03-24T15:51:35Z","timestamp":1774367495808,"version":"3.50.1"},"reference-count":47,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2017,7,1]],"date-time":"2017-07-01T00:00:00Z","timestamp":1498867200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,7,1]],"date-time":"2017-07-01T00:00:00Z","timestamp":1498867200000},"content-version":"am","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2017,7,1]],"date-time":"2017-07-01T00:00:00Z","timestamp":1498867200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2017,7,1]],"date-time":"2017-07-01T00:00:00Z","timestamp":1498867200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"DOI":"10.13039\/501100001744","name":"ISTC-CC","doi-asserted-by":"publisher","id":[{"id":"10.13039\/501100001744","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"US National Science Foundation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"name":"CAREER","award":["CCF-0953246"],"award-info":[{"award-number":["CCF-0953246"]}]},{"DOI":"10.13039\/100000001","name":"US National Science Foundation US National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1212962"],"award-info":[{"award-number":["CCF-1212962"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"US National Science Foundation US National Science Foundation","doi-asserted-by":"publisher","award":["CNS-1320531"],"award-info":[{"award-number":["CNS-1320531"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]},{"DOI":"10.13039\/100000001","name":"US National Science Foundation US National Science Foundation","doi-asserted-by":"publisher","award":["CCF-1566483"],"award-info":[{"award-number":["CCF-1566483"]}],"id":[{"id":"10.13039\/100000001","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2017,7,1]]},"DOI":"10.1109\/lca.2016.2624298","type":"journal-article","created":{"date-parts":[[2016,11,2]],"date-time":"2016-11-02T18:21:51Z","timestamp":1478110911000},"page":"88-93","source":"Crossref","is-referenced-by-count":22,"title":["A Case for Memory Content-Based Detection and Mitigation of Data-Dependent Failures in DRAM"],"prefix":"10.1109","volume":"16","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-0300-3034","authenticated-orcid":false,"given":"Samira","family":"Khan","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Chris","family":"Wilkerson","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Donghyuk","family":"Lee","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Alaa R.","family":"Alameldeen","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref39","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446095"},{"key":"ref38","doi-asserted-by":"publisher","DOI":"10.1145\/2540708.2540725"},{"key":"ref33","doi-asserted-by":"publisher","DOI":"10.1145\/2989081.2989114"},{"key":"ref32","first-page":"128","article-title":"Address and data scrambling: Causes and impact\n on memory tests","author":"schanstra","year":"0","journal-title":"Proc 1st IEEE Int Workshop Electron Des Test Appl"},{"key":"ref31","article-title":"Reducing DRAM latency by exploiting design-induced\n latency variation in modern DRAM chips","author":"lee","year":"2016"},{"key":"ref30","doi-asserted-by":"publisher","DOI":"10.1145\/1736020.1736064"},{"key":"ref37","article-title":"Standard Performance Evaluation Corporation","year":"0"},{"key":"ref36","doi-asserted-by":"publisher","DOI":"10.1145\/781027.781076"},{"key":"ref35","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2017.62"},{"key":"ref34","doi-asserted-by":"publisher","DOI":"10.1007\/978-1-4419-7958-2"},{"key":"ref10","first-page":"361","article-title":"Flipping bits in memory without accessing them: An\n experimental study of DRAM disturbance errors","author":"kim","year":"0","journal-title":"Proc 41st Annu Int Symp Comput Archit"},{"key":"ref40","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237032"},{"key":"ref11","first-page":"19","article-title":"Research problems and opportunities in memory systems","volume":"1","author":"mutlu","year":"2014","journal-title":"International Journal on Supercomputing Frontiers and Innovations"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2016.30"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1145\/2591971.2592000"},{"key":"ref14","year":"0"},{"key":"ref15","doi-asserted-by":"publisher","DOI":"10.1109\/VTEST.2004.1299234"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1109\/DFT.2014.6962069"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1145\/2485922.2485929"},{"key":"ref18","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2014.50"},{"key":"ref19","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.58"},{"key":"ref28","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2006.1598122"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1147\/rd.462.0187"},{"key":"ref27","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446096"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/IMW.2013.6582088"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609344"},{"key":"ref29","doi-asserted-by":"publisher","DOI":"10.1145\/1950365.1950391"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/IEDM.2005.1609340"},{"key":"ref8","article-title":"Co-architecting controllers and DRAM to\n enhance DRAM process scaling","author":"kang","year":"2014"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/2366231.2337161"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1109\/MTDT.2002.1029773"},{"key":"ref9","first-page":"60","article-title":"An experimental study of data retention behavior in modern DRAM devices:\n Implications for retention time profiling mechanisms","author":"liu","year":"0","journal-title":"Proc 40th Annu Int Symp Comput Archit"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/4.5933"},{"key":"ref46","article-title":"Memory performance attacks: Denial of memory service in multi-core systems","author":"moscibroda","year":"0","journal-title":"Proc 16th USENIX Security Symp"},{"key":"ref20","doi-asserted-by":"publisher","DOI":"10.1145\/1555349.1555372"},{"key":"ref45","year":"0"},{"key":"ref22","doi-asserted-by":"publisher","DOI":"10.1109\/SC.2012.13"},{"key":"ref47","first-page":"79","year":"2012","journal-title":"DDR3 SDRAM Specification"},{"key":"ref21","first-page":"111","article-title":"Cosmic rays don&#x2019;t strike twice: Understanding the nature of DRAM errors and the implications for\n system design","author":"hwang","year":"0","journal-title":"Proc Int Conf Archit Support Program Lang Oper Syst"},{"key":"ref42","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.51"},{"key":"ref24","doi-asserted-by":"publisher","DOI":"10.1145\/2694344.2694348"},{"key":"ref41","first-page":"615","article-title":"Tiered-latency DRAM: A low latency and low cost DRAM architecture","author":"lee","year":"0","journal-title":"Proc IEEE 19th Int Symp High Perform Comput Archit"},{"key":"ref23","doi-asserted-by":"publisher","DOI":"10.1109\/DSN.2015.57"},{"key":"ref44","year":"0"},{"key":"ref26","doi-asserted-by":"publisher","DOI":"10.1145\/2896377.2901453"},{"key":"ref43","year":"0"},{"key":"ref25","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2015.7056057"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/ieeexplore.ieee.org\/ielaam\/10208\/8240814\/7731210-aam.pdf","content-type":"application\/pdf","content-version":"am","intended-application":"syndication"},{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10208\/8240814\/07731210.pdf?arnumber=7731210","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,8]],"date-time":"2022-04-08T18:52:00Z","timestamp":1649443920000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7731210\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2017,7,1]]},"references-count":47,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/lca.2016.2624298","relation":{},"ISSN":["1556-6056"],"issn-type":[{"value":"1556-6056","type":"print"}],"subject":[],"published":{"date-parts":[[2017,7,1]]}}}