{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,12,17]],"date-time":"2025-12-17T18:00:11Z","timestamp":1765994411284,"version":"3.37.3"},"reference-count":11,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2018,1,1]],"date-time":"2018-01-01T00:00:00Z","timestamp":1514764800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"funder":[{"name":"Agency for Innovation by Science and Technology (IWT)"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2018,1,1]]},"DOI":"10.1109\/lca.2017.2701370","type":"journal-article","created":{"date-parts":[[2017,5,4]],"date-time":"2017-05-04T18:15:05Z","timestamp":1493921705000},"page":"9-12","source":"Crossref","is-referenced-by-count":12,"title":["Modeling Superscalar Processor Memory-Level Parallelism"],"prefix":"10.1109","volume":"17","author":[{"ORCID":"https:\/\/orcid.org\/0000-0003-3630-2214","authenticated-orcid":false,"given":"Sam","family":"Van Den Steen","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-8792-4473","authenticated-orcid":false,"given":"Lieven","family":"Eeckhout","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/2019608.2019609"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2004.1310786"},{"key":"ref10","article-title":"Sniper:\n Exploring the level of abstraction for scalable and accurate parallel multi-core simulation","author":"carlson","year":"2011","journal-title":"Proc Int Conf High Perform Comput Netw Storage Anal"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/PACT.2015.36"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1145\/1168857.1168880"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2012.23"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/ISPASS.2010.5452069"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/TC.2009.77"},{"key":"ref2","first-page":"32","article-title":"Micro-architecure\n independent analytical processor performance and power modeling","author":"van den steen","year":"2015","journal-title":"Proc IEEE Int Symp Perform Anal Syst Softw"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.1992.697004"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1028176.1006708"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10208\/8316264\/07919232.pdf?arnumber=7919232","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:28:12Z","timestamp":1642004892000},"score":1,"resource":{"primary":{"URL":"http:\/\/ieeexplore.ieee.org\/document\/7919232\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,1,1]]},"references-count":11,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/lca.2017.2701370","relation":{},"ISSN":["1556-6056"],"issn-type":[{"type":"print","value":"1556-6056"}],"subject":[],"published":{"date-parts":[[2018,1,1]]}}}