{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,2,21]],"date-time":"2025-02-21T13:30:39Z","timestamp":1740144639198,"version":"3.37.3"},"reference-count":14,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2018,7,1]],"date-time":"2018-07-01T00:00:00Z","timestamp":1530403200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2018,7,1]]},"DOI":"10.1109\/lca.2018.2827929","type":"journal-article","created":{"date-parts":[[2018,4,17]],"date-time":"2018-04-17T18:06:52Z","timestamp":1523988412000},"page":"143-146","source":"Crossref","is-referenced-by-count":2,"title":["Decoupled MapReduce for Shared-Memory Multi-Core Architectures"],"prefix":"10.1109","volume":"17","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-1403-6851","authenticated-orcid":false,"given":"Konstantinos","family":"Iliakis","sequence":"first","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0003-3151-2730","authenticated-orcid":false,"given":"Sotirios","family":"Xydis","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]},{"ORCID":"https:\/\/orcid.org\/0000-0002-6930-6847","authenticated-orcid":false,"given":"Dimitrios","family":"Soudris","sequence":"additional","affiliation":[],"role":[{"role":"author","vocabulary":"crossref"}]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/BigData.2013.6691563"},{"key":"ref11","doi-asserted-by":"publisher","DOI":"10.1109\/HPCSim.2012.6266938"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/TC.1979.1675439"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/ICSAMOS.2010.5642078"},{"year":"2013","author":"blechmann","key":"ref14"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1109\/TPDS.2010.158"},{"article-title":"Optimizing MapReduce\n for multicore architectures","year":"2010","author":"mao","key":"ref3"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2007.346181"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1145\/1723112.1723129"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2009.5306783"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1145\/384196.384222"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/1996092.1996095"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1145\/1327452.1327492"},{"key":"ref9","doi-asserted-by":"crossref","first-page":"523","DOI":"10.1145\/1854273.1854337","article-title":"Tiled-MapReduce: Optimizing resource usages of data-parallel applications on multicore with tiling","author":"chen","year":"2010","journal-title":"Proceedings of the 19th International Conference on Parallel Architectures and Compilation Techniques (PACT)"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10208\/8318337\/08340153.pdf?arnumber=8340153","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,1,12]],"date-time":"2022-01-12T16:18:16Z","timestamp":1642004296000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8340153\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2018,7,1]]},"references-count":14,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/lca.2018.2827929","relation":{},"ISSN":["1556-6056"],"issn-type":[{"type":"print","value":"1556-6056"}],"subject":[],"published":{"date-parts":[[2018,7,1]]}}}