{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2025,9,21]],"date-time":"2025-09-21T18:20:32Z","timestamp":1758478832516,"version":"3.37.3"},"reference-count":13,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"2","license":[{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2019,7,1]],"date-time":"2019-07-01T00:00:00Z","timestamp":1561939200000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"funder":[{"name":"DARPA DSSoC"},{"DOI":"10.13039\/100000028","name":"Semiconductor Research Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100000028","id-type":"DOI","asserted-by":"publisher"}]},{"name":"NSF","award":["CNS-1718160"],"award-info":[{"award-number":["CNS-1718160"]}]},{"DOI":"10.13039\/100002418","name":"Intel Corporation","doi-asserted-by":"publisher","id":[{"id":"10.13039\/100002418","id-type":"DOI","asserted-by":"publisher"}]}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2019,7,1]]},"DOI":"10.1109\/lca.2019.2910521","type":"journal-article","created":{"date-parts":[[2019,9,16]],"date-time":"2019-09-16T19:30:41Z","timestamp":1568662241000},"page":"119-123","source":"Crossref","is-referenced-by-count":6,"title":["Determining Optimal Coherency Interface for Many-Accelerator SoCs Using Bayesian Optimization"],"prefix":"10.1109","volume":"18","author":[{"ORCID":"https:\/\/orcid.org\/0000-0001-7076-9251","authenticated-orcid":false,"given":"Kshitij","family":"Bhardwaj","sequence":"first","affiliation":[]},{"given":"Marton","family":"Havasi","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7479-9263","authenticated-orcid":false,"given":"Yuan","family":"Yao","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-0662-7889","authenticated-orcid":false,"given":"David M.","family":"Brooks","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0001-7610-949X","authenticated-orcid":false,"given":"Jose Miguel Hernendez","family":"Lobato","sequence":"additional","affiliation":[]},{"given":"Gu-Yeon","family":"Wei","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1109\/ISLPED.2017.8009208"},{"key":"ref11","first-page":"97","article-title":"Aladdin: A pre-RTL, power-performance accelerator simulator enabling large design space exploration of customized architectures","author":"shao","year":"2014","journal-title":"Proc ACM\/IEEE 41st Int Symp Comput Archit"},{"key":"ref12","doi-asserted-by":"publisher","DOI":"10.1109\/MICRO.2016.7783751"},{"key":"ref13","first-page":"1015","article-title":"Gaussian process optimization in the bandit setting: No regret and experimental design","author":"srinivas","year":"2010","journal-title":"Proc 27th Int Conf Mach Learn"},{"key":"ref4","first-page":"202:1","article-title":"An analysis of accelerator coupling in heterogeneous architectures","author":"cota","year":"2015","journal-title":"Proc 52nd ACM\/EDAC\/IEEE Des Autom Conf"},{"key":"ref3","doi-asserted-by":"crossref","first-page":"1","DOI":"10.1145\/2024716.2024718","article-title":"The gem5 simulator","volume":"39","author":"binkert","year":"2011","journal-title":"SIGARCH Comput Archit News"},{"key":"ref6","doi-asserted-by":"publisher","DOI":"10.1109\/MM.2018.2877288"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/JPROC.2015.2494218"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1109\/5.726791"},{"key":"ref7","doi-asserted-by":"publisher","DOI":"10.1109\/NOCS.2018.8512153"},{"key":"ref2","first-page":"1","article-title":"Statistical performance of the ARM cortex A9 accelerator coherency port in the Xilinx Zynq SoC for real-time applications","author":"powell","year":"2015","journal-title":"ReConFig"},{"key":"ref1","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2018.00031"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1109\/IISWC.2014.6983050"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10208\/8748225\/08839929.pdf?arnumber=8839929","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,7,13]],"date-time":"2022-07-13T20:47:33Z","timestamp":1657745253000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/8839929\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2019,7,1]]},"references-count":13,"journal-issue":{"issue":"2"},"URL":"https:\/\/doi.org\/10.1109\/lca.2019.2910521","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"type":"print","value":"1556-6056"},{"type":"electronic","value":"1556-6064"},{"type":"electronic","value":"2473-2575"}],"subject":[],"published":{"date-parts":[[2019,7,1]]}}}