{"status":"ok","message-type":"work","message-version":"1.0.0","message":{"indexed":{"date-parts":[[2026,2,25]],"date-time":"2026-02-25T17:11:00Z","timestamp":1772039460544,"version":"3.50.1"},"reference-count":17,"publisher":"Institute of Electrical and Electronics Engineers (IEEE)","issue":"1","license":[{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"vor","delay-in-days":0,"URL":"https:\/\/ieeexplore.ieee.org\/Xplorehelp\/downloads\/license-information\/IEEE.html"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-029"},{"start":{"date-parts":[[2020,1,1]],"date-time":"2020-01-01T00:00:00Z","timestamp":1577836800000},"content-version":"stm-asf","delay-in-days":0,"URL":"https:\/\/doi.org\/10.15223\/policy-037"}],"content-domain":{"domain":[],"crossmark-restriction":false},"short-container-title":["IEEE Comput. Arch. Lett."],"published-print":{"date-parts":[[2020,1,1]]},"DOI":"10.1109\/lca.2020.2990599","type":"journal-article","created":{"date-parts":[[2020,4,28]],"date-time":"2020-04-28T00:13:53Z","timestamp":1588032833000},"page":"80-83","source":"Crossref","is-referenced-by-count":24,"title":["NoM: Network-on-Memory for Inter-Bank Data Transfer in Highly-Banked Memories"],"prefix":"10.1109","volume":"19","author":[{"ORCID":"https:\/\/orcid.org\/0000-0002-6310-8954","authenticated-orcid":false,"given":"Seyyed Hossein SeyyedAghaei","family":"Rezaei","sequence":"first","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-4117-7609","authenticated-orcid":false,"given":"Mehdi","family":"Modarressi","sequence":"additional","affiliation":[]},{"ORCID":"https:\/\/orcid.org\/0000-0002-1459-0852","authenticated-orcid":false,"given":"Rachata","family":"Ausavarungnirun","sequence":"additional","affiliation":[]},{"given":"Mohammad","family":"Sadrosadati","sequence":"additional","affiliation":[]},{"given":"Onur","family":"Mutlu","sequence":"additional","affiliation":[]},{"given":"Masoud","family":"Daneshtalab","sequence":"additional","affiliation":[]}],"member":"263","reference":[{"key":"ref10","doi-asserted-by":"publisher","DOI":"10.1145\/2832911"},{"key":"ref11","doi-asserted-by":"crossref","first-page":"5","DOI":"10.1109\/LCA.2015.2448532","article-title":"Dynamic resource sharing for high-performance 3-D networks-on-chip","volume":"15","author":"seyyedaghaei","year":"2016","journal-title":"IEEE Computer Architecture Letters"},{"key":"ref12","first-page":"1195","article-title":"Fault-tolerant 3-D network-on-chip deign using dynamic link sharing","author":"seyyedaghaei","year":"2016","journal-title":"Proc Design Autom Test Eur Conf Exhib"},{"key":"ref13","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2414456"},{"key":"ref14","year":"0"},{"key":"ref15","article-title":"Calculating Memory System Power for DDR3","year":"2007"},{"key":"ref16","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001178"},{"key":"ref17","doi-asserted-by":"publisher","DOI":"10.1109\/ISCA.2012.6237032"},{"key":"ref4","doi-asserted-by":"publisher","DOI":"10.1145\/3007787.3001191"},{"key":"ref3","doi-asserted-by":"publisher","DOI":"10.1109\/HPCA.2016.7446095"},{"key":"ref6","first-page":"145","article-title":"Memory-centric system interconnect design with hybrid memory cubes","author":"kim","year":"2013","journal-title":"Proc Int Conf Parallel Archit Compilation Tech"},{"key":"ref5","doi-asserted-by":"publisher","DOI":"10.1109\/LCA.2015.2434872"},{"key":"ref8","doi-asserted-by":"publisher","DOI":"10.1145\/1555754.1555781"},{"key":"ref7","article-title":"Hybrid Memory Cube Consortium, Hybrid Memory Cube Specification Version 2.1","year":"2015"},{"key":"ref2","doi-asserted-by":"publisher","DOI":"10.1145\/3123939.3124544"},{"key":"ref1","first-page":"185","article-title":"RowClone: Fast and Energy-Efficient in-DRAM Bulk Data Copy and Initialization","author":"vivek seshadri","year":"2013","journal-title":"2013 46th Annual IEEE\/ACM International Symposium on Microarchitecture (MICRO)"},{"key":"ref9","doi-asserted-by":"publisher","DOI":"10.1007\/s11227-014-1337-0"}],"container-title":["IEEE Computer Architecture Letters"],"original-title":[],"link":[{"URL":"http:\/\/xplorestaging.ieee.org\/ielx7\/10208\/8968801\/09078774.pdf?arnumber=9078774","content-type":"unspecified","content-version":"vor","intended-application":"similarity-checking"}],"deposited":{"date-parts":[[2022,4,27]],"date-time":"2022-04-27T17:01:08Z","timestamp":1651078868000},"score":1,"resource":{"primary":{"URL":"https:\/\/ieeexplore.ieee.org\/document\/9078774\/"}},"subtitle":[],"short-title":[],"issued":{"date-parts":[[2020,1,1]]},"references-count":17,"journal-issue":{"issue":"1"},"URL":"https:\/\/doi.org\/10.1109\/lca.2020.2990599","relation":{},"ISSN":["1556-6056","1556-6064","2473-2575"],"issn-type":[{"value":"1556-6056","type":"print"},{"value":"1556-6064","type":"electronic"},{"value":"2473-2575","type":"electronic"}],"subject":[],"published":{"date-parts":[[2020,1,1]]}}}